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| author | Arnd Bergmann <arnd@arndb.de> | 2024-09-11 09:03:44 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-09-11 09:03:44 +0000 |
| commit | 3c557d0062bc73e430d496710819bc63ded439ca (patch) | |
| tree | 0b415f81556afe90c8d314fb20221d7283e36d80 | |
| parent | e4a82810c685f21eb617e1aab3c0b93e03ca6def (diff) | |
| parent | 72160ec6cb12613663f26d89049b95f8dc9fa000 (diff) | |
Merge tag 'riscv-config-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/defconfig
RISC-V config for v6.12
Two patches, enabling clock and pinctrl support in defconfig for Sopghgo
devices.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-config-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: defconfig: Enable pinctrl support for CV18XX Series SoC
riscv: defconfig: sophgo: enable clks for sg2042
Link: https://lore.kernel.org/r/20240910-annex-ravage-07d63041a7c5@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/riscv/configs/defconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 0d678325444f..ee978cc74673 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -167,6 +167,10 @@ CONFIG_SPI_RSPI=m CONFIG_SPI_SIFIVE=y CONFIG_SPI_SUN6I=y # CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL_SOPHGO_CV1800B=y +CONFIG_PINCTRL_SOPHGO_CV1812H=y +CONFIG_PINCTRL_SOPHGO_SG2000=y +CONFIG_PINCTRL_SOPHGO_SG2002=y CONFIG_GPIO_SIFIVE=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_SENSORS_SFCTEMP=m @@ -249,6 +253,9 @@ CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y CONFIG_CLK_SOPHGO_CV1800=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y +CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y +CONFIG_CLK_SOPHGO_SG2042_RPGATE=y CONFIG_SUN8I_DE2_CCU=m CONFIG_RENESAS_OSTM=y CONFIG_SUN50I_IOMMU=y |