diff options
| author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-17 10:30:40 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-07-20 17:22:30 +0100 |
| commit | 3e6670a28b009cc381b40ee26a6f41509aca46eb (patch) | |
| tree | 452792bdd82c09844dc1d0d726118239d012e6a3 | |
| parent | 3fcbcfc496f0cc08f9dc004a92915ce1cfb7ea95 (diff) | |
riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node
Add PLL clocks input from PLL clocks driver in SYSCRG node.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 0cfa66e71963..7f02b8b8287d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -517,12 +517,16 @@ <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL1_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; }; |