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authorPaolo Bonzini <pbonzini@redhat.com>2025-11-13 19:36:25 -0500
committerSean Christopherson <seanjc@google.com>2025-11-19 14:25:59 -0800
commit3f3fc58df502567fb26703276691299c2b712996 (patch)
treeef18939db8cf3532d587b09ba44ac169406e7a9a
parentc57d9bafbd0b89709c1bbbda346cf81dea5a3224 (diff)
KVM: x86: Move Src2Shift up one bit (use bits 36:32 for Src2 in the emulator)
An irresistible microoptimization (changing accesses to Src2 to just an AND :)) that also frees a bit for AVX in the low flags word. This makes it closer to SSE since both of them can access XMM registers, pointlessly shaving another clock cycle or two (maybe). No functional change intended. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Chang S. Bae <chang.seok.bae@intel.com Link: https://patch.msgid.link/20251114003633.60689-3-pbonzini@redhat.com Signed-off-by: Sean Christopherson <seanjc@google.com>
-rw-r--r--arch/x86/kvm/emulate.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 43ae4fcb2137..57799b5d9da2 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -147,7 +147,7 @@
#define PageTable (1 << 29) /* instruction used to write page table */
#define NotImpl (1 << 30) /* instruction is not implemented */
/* Source 2 operand type */
-#define Src2Shift (31)
+#define Src2Shift (32) /* bits 32-36 */
#define Src2None (OpNone << Src2Shift)
#define Src2Mem (OpMem << Src2Shift)
#define Src2CL (OpCL << Src2Shift)
@@ -161,6 +161,7 @@
#define Src2FS (OpFS << Src2Shift)
#define Src2GS (OpGS << Src2Shift)
#define Src2Mask (OpMask << Src2Shift)
+/* free: 37-39 */
#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
#define AlignMask ((u64)7 << 41)
#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */