diff options
| author | Frank Li <Frank.Li@nxp.com> | 2024-10-01 14:37:47 -0400 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2024-10-21 16:24:08 +0800 |
| commit | 4a0dc71f7bde15fde010224ecef99ef95c4f1f4c (patch) | |
| tree | 65759c87e523b5c28e0121f13d4fa281b2c07a33 | |
| parent | a8fe6c8dfc40ccfa4d4d001858e9d4b42e14ff84 (diff) | |
arm64: dts: imx8mp-evk: add PCIe Endpoint function overlay file
PCIe of i.MX8MP is dual role PCIe controller, which can work as root
complex (RC) mode and endpoint (EP) mode. Add overlay file to let it work
as EP mode.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso | 17 |
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 13d6ba52bf3c..0377e0969ce9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -210,7 +210,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo +imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso new file mode 100644 index 000000000000..244e820699b5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; +/plugin/; + +&pcie { + status = "disabled"; +}; + +&pcie_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + status = "okay"; +}; |