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| author | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2025-07-03 12:24:59 +0200 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2025-07-08 18:35:50 +0100 |
| commit | 4edcfaf951a28b0663f4e05222d00ac992fab82c (patch) | |
| tree | 9ae6fa14da7291a6e3824645541c7cf8dfe24299 | |
| parent | 3037134b1b627afce46669a781a8e9d42437de4c (diff) | |
arm64/sysreg: Add ICC_CR0_EL1
Add ICC_CR0_EL1 register description.
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-9-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
| -rw-r--r-- | arch/arm64/tools/sysreg | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 78a51fbf3a99..ebbb22ed2301 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3519,6 +3519,14 @@ Res0 14:12 Field 11:0 AFFINITY EndSysreg +Sysreg ICC_CR0_EL1 3 1 12 0 1 +Res0 63:39 +Field 38 PID +Field 37:32 IPPT +Res0 31:1 +Field 0 EN +EndSysreg + Sysreg CSSELR_EL1 3 2 0 0 0 Res0 63:5 Field 4 TnD |