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authorAmadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>2024-10-14 11:49:58 +0200
committerTakashi Iwai <tiwai@suse.de>2024-10-14 12:00:52 +0200
commit52345d35622026b99271edc1c58ad7cfef3b7567 (patch)
treec604156480140b397656c74318773fc89ead7c45
parent0ddf2784d6c29e59409a62b8f32dc5abe56135a4 (diff)
ALSA: hda: Fix all stream interrupts definition
It is defined in header to 0xFF, which only allows to set values for 8 streams. In specification it is defined as bits from 0 to 29. In practice there is no HW with 29 streams, but as the only place where the value is used is chip initialization, it is best to make sure that all bits are reset properly. Reviewed-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com> Link: https://patch.msgid.link/20241014094958.708563-1-amadeuszx.slawinski@linux.intel.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
-rw-r--r--include/sound/hda_register.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h
index 5ff31e6d41c1..db1cc0b897fd 100644
--- a/include/sound/hda_register.h
+++ b/include/sound/hda_register.h
@@ -180,7 +180,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
/* INTCTL and INTSTS */
-#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */
+#define AZX_INT_ALL_STREAM 0x3fffffff /* all stream interrupts */
#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */