diff options
| author | Aaron Kling <webgeek1234@gmail.com> | 2025-09-06 15:16:52 -0500 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-09-10 11:40:25 +0200 |
| commit | 550faad18505aac40a1551a5b467e0a63bf2d639 (patch) | |
| tree | 8ae9a82abf61939e7232e07be86b389ceeb2df8f | |
| parent | 1aba1eab0bd896928ae20dbf1f60a175a6e1ad0f (diff) | |
dt-bindings: memory: tegra210: emc: Document OPP table and interconnect
These are needed for dynamic frequency scaling of the EMC controller.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml index bc8477e7ab19..4e4fb4acd7f9 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml @@ -33,6 +33,9 @@ properties: items: - description: EMC general interrupt + "#interconnect-cells": + const: 0 + memory-region: maxItems: 1 description: @@ -44,6 +47,11 @@ properties: description: phandle of the memory controller node + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + required: - compatible - reg @@ -79,4 +87,7 @@ examples: interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; memory-region = <&emc_table>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + + #interconnect-cells = <0>; }; |