diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2025-11-23 18:53:43 +0000 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-11-25 22:12:59 +0000 |
| commit | 56dfdf2da1cf6261eaeb4259dee27201f2800691 (patch) | |
| tree | f5f67a743350f32dc4abf501d55dd6ca0d631f74 | |
| parent | 76cc0ba2af91c88d36adb4d0a3d5529726353051 (diff) | |
MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes
The SiFive and Canaan platforms are not being actively looked after at
this point, but fixes for them would be applied if/when the patches
appeared. Since they're now the only things in the RISC-V MISC SOC
SUPPORT, mark them as Odd Fixes. I don't believe this is a functional
change, it just represents what's actually happening - particularly
since the Canaan k230 never built up enough steam to get merged and the
new SiFive demo chips have been done in partnership with with other
companies, e.g. Eswin, and will reside in their directories instead.
Reviewed-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | MAINTAINERS | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 4981224985b4..72bfa33aa225 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22115,7 +22115,7 @@ F: include/soc/microchip/mpfs.h RISC-V MISC SOC SUPPORT M: Conor Dooley <conor@kernel.org> L: linux-riscv@lists.infradead.org -S: Maintained +S: Odd Fixes T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: arch/riscv/boot/dts/canaan/ F: arch/riscv/boot/dts/sifive/ |