diff options
| author | Lorenzo Bianconi <lorenzo@kernel.org> | 2024-06-29 19:51:48 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2024-07-02 18:54:28 +0530 |
| commit | 5854d0aa5226816575d2323e95bffdc9267d78b1 (patch) | |
| tree | a58738a8d0460f31814f475831d41cad6e807597 | |
| parent | e245c725c72f8c94e5fe435fdefd6852851450b5 (diff) | |
dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers
Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581
PCIe-PHY binding. This change is not introducing any backward compatibility
issue since the EN7581 dts is not upstream yet.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/a018329ff9678f3360bc6381294f95c62d34f3e3.1719682943.git.lorenzo@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml index e26c30d17ff0..98fcb1b364de 100644 --- a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml @@ -21,12 +21,18 @@ properties: - description: PCIE analog base address - description: PCIE lane0 base address - description: PCIE lane1 base address + - description: PCIE lane0 detection time base address + - description: PCIE lane1 detection time base address + - description: PCIE Rx AEQ base address reg-names: items: - const: csr-2l - const: pma0 - const: pma1 + - const: p0-xr-dtime + - const: p1-xr-dtime + - const: rx-aeq "#phy-cells": const: 0 @@ -52,7 +58,12 @@ examples: #phy-cells = <0>; reg = <0x0 0x1fa5a000 0x0 0xfff>, <0x0 0x1fa5b000 0x0 0xfff>, - <0x0 0x1fa5c000 0x0 0xfff>; - reg-names = "csr-2l", "pma0", "pma1"; + <0x0 0x1fa5c000 0x0 0xfff>, + <0x0 0x1fc10044 0x0 0x4>, + <0x0 0x1fc30044 0x0 0x4>, + <0x0 0x1fc15030 0x0 0x104>; + reg-names = "csr-2l", "pma0", "pma1", + "p0-xr-dtime", "p1-xr-dtime", + "rx-aeq"; }; }; |