diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-12 01:19:29 +0200 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2025-03-04 15:39:23 +0100 |
| commit | 600a0c7e76bb28244e019da3d6a42cae0c836f60 (patch) | |
| tree | cac1ea92f737e28a0af603a91c4fcde9ed55878c | |
| parent | 7ded94bd11d47a8ddef051aef1d1a42d8191e09f (diff) | |
drm/i915: Bump RING_FAULT engine ID bits
The fault engine ID field has been 5 bits since icl. Bump our
define to match. The extra bits were unused before icl so we
should be able to use the larger mask unconditionally.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-2-ville.syrjala@linux.intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a6e50af44b46..424b7ff9dbf2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1044,7 +1044,7 @@ #define GEN12_RING_FAULT_REG _MMIO(0xcec4) #define XEHP_RING_FAULT_REG MCR_REG(0xcec4) #define XELPMP_RING_FAULT_REG _MMIO(0xcec4) -#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) +#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x1f) #define RING_FAULT_GTTSEL_MASK (1 << 11) #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) |