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authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2025-08-22 15:33:19 +0200
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2025-08-31 12:59:18 +0200
commit613fb0c8bd49df4fb28bca89aa5363856487096f (patch)
tree868fb734d2c984254897e282e34b6222a05b1655
parent8f5ae30d69d7543eee0d70083daf4de8fe15d585 (diff)
arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells
Add missing address-cells 0 to the PCI interrupt node to silence W=1 warning: uniphier-ld20.dtsi:941.4-944.29: Warning (interrupt_map): /soc@0/pcie@66000000:interrupt-map: Missing property '#address-cells' in node /soc@0/pcie@66000000/legacy-interrupt-controller, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20250822133318.312232-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 335093da6573..875b93856a64 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -947,6 +947,7 @@
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;