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| author | Junhui Liu <junhui.liu@pigmoral.tech> | 2025-10-21 17:41:37 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-11-12 17:06:56 +0000 |
| commit | 66c2a3173cdaf7b776552203609f008c8709dd22 (patch) | |
| tree | 86dc21f8e0ebbe8945bec0b67f6778ce429afe3d | |
| parent | c86ee66e14acb15d7d20b329ea49f751c9df8bc9 (diff) | |
dt-bindings: riscv: Add Nuclei UX900 compatibles
The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC.
It features a 64-bit architecture and dual-issue, 9-stage pipeline, with
lots of optional extensions including V, K, Zc, and more.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 153d0dac57fb..20b7c834559c 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -48,6 +48,7 @@ properties: - amd,mbv64 - andestech,ax45mp - canaan,k210 + - nuclei,ux900 - sifive,bullet0 - sifive,e5 - sifive,e7 |