diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-01-23 10:08:18 +0200 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-01-24 10:22:59 +0200 |
| commit | 6c021d77e788aa046845e9877753a7a1148b24b3 (patch) | |
| tree | 2ea1ae8c4ec3e81699cd6485e568016b18dfe83a | |
| parent | 31c318051040a8d60d027ae64182f04155c15737 (diff) | |
drm/msm/dpu: fix sm8450 CTL configuration
Correct the CTL size on sm8450 platform. This fixes the incorrect merge
of sm8350 support, which unfortunately also touched the SM8450 setup.
Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/519671/
Link: https://lore.kernel.org/r/20230123080818.3069266-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index e277c8450ccd..404a14d28bfc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -972,31 +972,31 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = { }, { .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x1e8, + .base = 0x16000, .len = 0x204, .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x1e8, + .base = 0x17000, .len = 0x204, .features = CTL_SC7280_MASK, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x1e8, + .base = 0x18000, .len = 0x204, .features = CTL_SC7280_MASK, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x1e8, + .base = 0x19000, .len = 0x204, .features = CTL_SC7280_MASK, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x1e8, + .base = 0x1a000, .len = 0x204, .features = CTL_SC7280_MASK, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, |