diff options
| author | Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com> | 2024-10-23 10:21:08 +0000 |
|---|---|---|
| committer | Mario Limonciello <mario.limonciello@amd.com> | 2024-10-28 14:54:36 -0500 |
| commit | 73070a9169b16e08b191066e513bce6c237c9221 (patch) | |
| tree | fb8812245ba83253e2d3a4271a1125278ad8a608 | |
| parent | 7fb463aac84577b93f666658ef61e59d78c53627 (diff) | |
cpufreq/amd-pstate: Do not attempt to clear MSR_AMD_CPPC_ENABLE
MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear
it is futile, it will not take effect. Hence, return if disable (0)
argument is passed to the msr_cppc_enable()
Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
Link: https://lore.kernel.org/r/20241023102108.5980-3-Dhananjay.Ugwekar@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
| -rw-r--r-- | drivers/cpufreq/amd-pstate.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 0b4a4d69c14d..576251e61ce0 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -311,6 +311,12 @@ static inline int msr_cppc_enable(bool enable) int ret, cpu; unsigned long logical_proc_id_mask = 0; + /* + * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared. + */ + if (!enable) + return 0; + if (enable == cppc_enabled) return 0; |