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authorJingbao Qiu <qiujingbao.dlmu@gmail.com>2025-03-15 23:49:12 +0100
committerInochi Amaoto <inochiama@gmail.com>2025-05-07 08:35:34 +0800
commit76517429dbfd8eca16fe85482cdb8024bbbd06bd (patch)
tree7d4683d4a17b09ac581588e210a4e8722121ef19
parentf18198c0de56ea636c74312bd09b9d67273412d8 (diff)
dt-bindings: soc: sophgo: add RTC support for Sophgo CV1800 series
Add RTC devicetree binding for Sophgo CV1800 series SoC. The device is called RTC, but contains control registers of other HW blocks in its address space, most notably of Power-on-Reset (PoR) module, DW8051 IP (MCU core), accompanying SRAM, hence putting it in SoC subsystem. Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20250315224921.3627852-2-alexander.sverdlin@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
-rw-r--r--Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml86
1 files changed, 86 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml
new file mode 100644
index 000000000000..5cf186c396c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sophgo/sophgo,cv1800b-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Real Time Clock of the Sophgo CV1800 SoC
+
+description:
+ The RTC (Real Time Clock) is an independently powered module in the chip. It
+ contains a 32KHz oscillator and a Power-On-Reset (POR) sub-module, which can
+ be used for time display and scheduled alarm produce. In addition, the
+ hardware state machine provides triggering and timing control for chip
+ power-on, power-off and reset.
+
+ Furthermore, the 8051 subsystem is located within RTCSYS and is independently
+ powered. System software can use the 8051 to manage wake conditions and wake
+ the system while the system is asleep, and communicate with external devices
+ through peripheral controllers.
+
+ Technical Reference Manual available at
+ https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM
+
+maintainers:
+ - sophgo@lists.linux.dev
+
+allOf:
+ - $ref: /schemas/rtc/rtc.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: sophgo,cv1800b-rtc
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: RTC Alarm
+ - description: RTC Longpress
+ - description: VBAT DET
+
+ interrupt-names:
+ items:
+ - const: alarm
+ - const: longpress
+ - const: vbat
+
+ clocks:
+ items:
+ - description: RTC clock source
+ - description: DW8051 MCU clock source
+
+ clock-names:
+ items:
+ - const: rtc
+ - const: mcu
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sophgo,cv1800.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ rtc@5025000 {
+ compatible = "sophgo,cv1800b-rtc", "syscon";
+ reg = <0x5025000 0x2000>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>,
+ <19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "alarm", "longpress", "vbat";
+ clocks = <&clk CLK_RTC_25M>,
+ <&clk CLK_SRC_RTC_SYS_0>;
+ clock-names = "rtc", "mcu";
+ };