diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2023-02-13 15:47:21 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-02-13 15:47:52 +0100 |
| commit | 7dbdc16fc85bcd89a2f3698df37a7202ea266454 (patch) | |
| tree | 7328e118d60b327e612f32d9bfe28f4fd96ba4c6 | |
| parent | fc54e13d712501cd2ad99ac015c5ff8a0c6ae184 (diff) | |
| parent | f069ede81ef438d99e76112d8738c4dc3d1766f9 (diff) | |
Merge tag 'qcom-arm64-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
More Qualcomm ARM64 DT updates for 6.3
The new Qualcomm QDU1000 and QRU1000 platforms, and the IDP device on
these are introduced. New support for a couple of USB modem sticks from
THWC are introduced, so is support for Xiaomi Mi Pad 5 Pro and the Pro
SKU of the Herobrine device.
The Core Bus Fabric (CBF) is introduced on MSM8996. Interconnect paths
for UFS are also described.
A few fixes related to the power-grid of herobrine, on SC7280, are
introduced.
QFPROM is introduced on IPQ8074 and Interconnect providers are added for
SDM670.
On SDM845 the duplicated wcd9340 audio coded description is moved from
devices to a common file, audio devices are added to the OnePlus 6 and
6T.
On SM6115 debug UART, SMP2P, watchdog nodes are introduced, and the
platform is switched to use #address/size-cells of 2, in line with most
other platforms.
Camera control interface and clock controllers are added for SM6350, and
the CCI interface is enabled on the Fairphone FP4.
On SM8350 the interconnect reference of SDHCI controller is corrected,
DSI1 PHY clocks are properly described as sources for the Display clock
controller and DSI1 is wired up to the display controller.
The firmware paths are corrected for the Sony Xperia Nagara platform.
The GPR bus, audio servic3es and LPASS pinctrl nodes are added for the
SM8550 platform. Additionally a few small typos/errors are corrected.
gpio-ranges are corrected across MSM8953, SM6115 and SC8280XP and a
range of DT validation issues are corrected.
* tag 'qcom-arm64-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (81 commits)
arm64: dts: qcom: sc7280: Power herobrine's 3.3 eDP/TS rail more properly
arm64: dts: qcom: pmk8550: fix PON compatible
arm64: dts: qcom: sm8550: fix DSI controller compatible
arm64: dts: qcom: sc7280: Hook up the touchscreen IO rail on evoker
arm64: dts: qcom: sc7280: Hook up the touchscreen IO rail on villager
arm64: dts: qcom: sc7280: Add 3ms ramp to herobrine's pp3300_left_in_mlb
arm64: dts: qcom: sc7280: On QCard, regulator L3C should be 1.8V
arm64: dts: qcom: sc8280xp: correct LPASS GPIO gpio-ranges
arm64: dts: qcom: msm8992-lg-bullhead: Enable regulators
arm64: dts: qcom: sm6115: correct TLMM gpio-ranges
arm64: dts: qcom: msm8953: correct TLMM gpio-ranges
arm64: dts: qcom: msm8992-lg-bullhead: Correct memory overlaps with the SMEM and MPSS memory regions
arm64: dts: qcom: sm8350-hdk: correct LT9611 pin function
arm64: dts: qcom: sm8350-hdk: align pin config node names with bindings
arm64: dts: qcom: sm6350: Use specific qmpphy compatible
arm64: dts: qcom: sm6115: Add smp2p nodes
arm64: dts: qcom: sm7225-fairphone-fp4: Enable CCI busses
arm64: dts: qcom: sm6350: Add CCI nodes
arm64: dts: qcom: sm6350: Add camera clock controller
dt-bindings: clock: add QCOM SM6350 camera clock bindings
...
Link: https://lore.kernel.org/r/20230210192908.2039976-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
80 files changed, 6086 insertions, 461 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml new file mode 100644 index 000000000000..767a9d03aa32 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 + +maintainers: + - Melody Olvera <quic_molvera@quicinc.com> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on QDU1000 and QRU1000 + + See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h + +properties: + compatible: + const: qcom,qdu1000-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 0 Phy Auxiliary clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,qdu1000-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>, + <&usb3_phy_wrapper_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml new file mode 100644 index 000000000000..fd6658cb793d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6350-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM6350 + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SM6350. + + See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h + +properties: + compatible: + const: qcom,sm6350-camcc + + clocks: + items: + - description: Board XO source + + reg: + maxItems: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ad00000 { + compatible = "qcom,sm6350-camcc"; + reg = <0x0ad00000 0x16000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml new file mode 100644 index 000000000000..0070b0396e31 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000 + +maintainers: + - Georgi Djakov <djakov@kernel.org> + - Odelu Kukatla <quic_okukatla@quicinc.com> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + compatible: + enum: + - qcom,qdu1000-clk-virt + - qcom,qdu1000-gem-noc + - qcom,qdu1000-mc-virt + - qcom,qdu1000-system-noc + + '#interconnect-cells': true + + reg: + maxItems: 1 + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,qdu1000-clk-virt + - qcom,qdu1000-mc-virt + then: + properties: + reg: false + else: + required: + - reg + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> + + system_noc: interconnect@1640000 { + compatible = "qcom,qdu1000-system-noc"; + reg = <0x1640000 0x45080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,qdu1000-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0423ca3e79f..31aa54f0428c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -25,6 +25,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt58.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5x.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb @@ -66,8 +68,10 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb @@ -123,6 +127,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd-pro.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb @@ -184,6 +189,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 0e3d1d906a22..62d05d740646 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -266,6 +266,13 @@ status = "disabled"; }; + qfprom: efuse@a4000 { + compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + }; + prng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts new file mode 100644 index 000000000000..c492db856190 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-ufi.dtsi" + +/ { + model = "uf896 4G Modem Stick"; + compatible = "thwc,uf896", "qcom,msm8916"; +}; + +&button_restart { + gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; +}; + +&led_r { + gpios = <&msmgpio 82 GPIO_ACTIVE_HIGH>; +}; + +&led_g { + gpios = <&msmgpio 83 GPIO_ACTIVE_HIGH>; +}; + +&led_b { + gpios = <&msmgpio 81 GPIO_ACTIVE_HIGH>; +}; + +&button_default { + pins = "gpio35"; + bias-pull-up; +}; + +&gpio_leds_default { + pins = "gpio81", "gpio82", "gpio83"; +}; + +&sim_ctrl_default { + pins = "gpio1", "gpio2"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts new file mode 100644 index 000000000000..700cf81cbf8c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-ufi.dtsi" + +/ { + model = "ufi-001c/ufi-001b 4G Modem Stick"; + compatible = "thwc,ufi001c", "qcom,msm8916"; +}; + +&button_restart { + gpios = <&msmgpio 37 GPIO_ACTIVE_HIGH>; +}; + +&led_r { + gpios = <&msmgpio 22 GPIO_ACTIVE_HIGH>; +}; + +&led_g { + gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; +}; + +&led_b { + gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; +}; + +&button_default { + pins = "gpio37"; + bias-pull-down; +}; + +&gpio_leds_default { + pins = "gpio20", "gpio21", "gpio22"; +}; + +&sim_ctrl_default { + pins = "gpio1", "gpio2"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi new file mode 100644 index 000000000000..790a9696da9d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-pm8916.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + chassis-type = "embedded"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + mpss_mem: mpss@86800000 { + reg = <0x0 0x86800000 0x0 0x5500000>; + no-map; + }; + + gps_mem: gps@8bd00000 { + reg = <0x0 0x8bd00000 0x0 0x200000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&button_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + /* GPIO is board-specific */ + button_restart: button-restart { + label = "Restart"; + linux,code = <KEY_RESTART>; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + /* + * GPIOs are board-specific. + * Functions and default-states defined here are fallbacks. + * Feel free to override them if your board is different. + */ + led_r: led-r { + color = <LED_COLOR_ID_RED>; + default-state = "on"; + function = LED_FUNCTION_POWER; + }; + + led_g: led-g { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_WLAN; + }; + + led_b: led-b { + color = <LED_COLOR_ID_BLUE>; + default-state = "off"; + function = LED_FUNCTION_WAN; + }; + }; +}; + +&bam_dmux { + status = "okay"; +}; + +&bam_dmux_dma { + status = "okay"; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +/* Remove &dsi_phy0 from clocks to make sure that gcc probes with display disabled */ +&gcc { + clocks = <&xo_board>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>; +}; + +&mpss { + pinctrl-0 = <&sim_ctrl_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pm8916_usbin { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&usb { + extcon = <&pm8916_usbin>; + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&pm8916_usbin>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + /* pins are board-specific */ + button_default: button-default-state { + function = "gpio"; + drive-strength = <2>; + }; + + gpio_leds_default: gpio-leds-default-state { + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sim_ctrl_default: sim-ctrl-default-state { + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 4e17bc9f8167..610f3e3fc0c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -399,7 +399,7 @@ reg = <0x1000000 0x300000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; - gpio-ranges = <&tlmm 0 0 155>; + gpio-ranges = <&tlmm 0 0 142>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index 4bceb362a5c0..cd77dcb55872 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -56,8 +56,13 @@ no-map; }; - removed_region: reserved@5000000 { - reg = <0 0x05000000 0 0x2200000>; + reserved@5000000 { + reg = <0x0 0x05000000 0x0 0x1a00000>; + no-map; + }; + + reserved@6c00000 { + reg = <0x0 0x06c00000 0x0 0x400000>; no-map; }; }; @@ -89,8 +94,8 @@ /* S1, S2, S6 and S12 are managed by RPMPD */ pm8994_s1: s1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; }; pm8994_s2: s2 { @@ -246,11 +251,8 @@ }; pm8994_l26: l26 { - /* - * TODO: value from downstream - * regulator-min-microvolt = <987500>; - * fails to apply - */ + regulator-min-microvolt = <987500>; + regulator-max-microvolt = <987500>; }; pm8994_l27: l27 { @@ -264,19 +266,13 @@ }; pm8994_l29: l29 { - /* - * TODO: Unsupported voltage range. - * regulator-min-microvolt = <2800000>; - * regulator-max-microvolt = <2800000>; - */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; }; pm8994_l30: l30 { - /* - * TODO: get this verified - * regulator-min-microvolt = <1800000>; - * regulator-max-microvolt = <1800000>; - */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; pm8994_l31: l31 { @@ -285,11 +281,8 @@ }; pm8994_l32: l32 { - /* - * TODO: get this verified - * regulator-min-microvolt = <1800000>; - * regulator-max-microvolt = <1800000>; - */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 5b47b8de69da..2acfed28e3cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -229,7 +229,7 @@ status = "okay"; label = "QCA_UART"; - bluetooth: qca6174a { + bluetooth: bluetooth { compatible = "qcom,qca6174-bt"; enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 55180586f7b6..6f180a8efe77 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -719,7 +719,7 @@ #power-domain-cells = <1>; reg = <0x00300000 0x90000>; - clocks = <&rpmcc RPM_SMD_BB_CLK1>, + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_LN_BB_CLK>, <&sleep_clk>, <&pciephy_0>, @@ -1061,7 +1061,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; status = "disabled"; }; @@ -1129,7 +1129,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; status = "disabled"; }; @@ -2037,6 +2037,10 @@ <0 0>, <0 0>; + interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + lanes-per-direction = <1>; #reset-cells = <1>; status = "disabled"; @@ -2958,7 +2962,7 @@ reg = <0x06400000 0x90000>; clock-names = "xo", "sys_apcs_aux"; - clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&apcs_glb>; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; #clock-cells = <1>; }; @@ -3077,7 +3081,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&rpmcc RPM_SMD_BB_CLK1>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; resets = <&gcc GCC_SDCC1_BCR>; pinctrl-names = "default", "sleep"; @@ -3101,7 +3105,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmcc RPM_SMD_BB_CLK1>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; resets = <&gcc GCC_SDCC2_BCR>; pinctrl-names = "default", "sleep"; @@ -3423,7 +3427,7 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - clocks = <&rpmcc RPM_SMD_BB_CLK1>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; memory-region = <&adsp_mem>; @@ -3568,6 +3572,13 @@ reg = <0x09a10000 0x1000>; }; + cbf: clock-controller@9a11000 { + compatible = "qcom,msm8996-cbf"; + reg = <0x09a11000 0x10000>; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; + #clock-cells = <0>; + }; + intc: interrupt-controller@9bc0000 { compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index 47213d05bf92..201efeda7d2d 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -16,7 +16,7 @@ #size-cells = <0>; pmk8550_pon: pon@1300 { - compatible = "qcom,pm8998-pon"; + compatible = "qcom,pmk8350-pon"; reg = <0x1300>, <0x800>; reg-names = "hlos", "pbs"; diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts new file mode 100644 index 000000000000..9e9fd4b8023e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "qdu1000.dtsi" +#include "pm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QDU1000 IDP"; + compatible = "qcom,qdu1000-idp", "qcom,qdu1000"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; +}; + +&apps_rsc { + regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vph_pwr>; + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; + vdd-l6-l9-supply = <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply = <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name = "vreg_s2a_0p5"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name = "vreg_s3a_1p05"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name = "vreg_s6a_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name = "vreg_s7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name = "vreg_s8a_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name = "vreg_l1a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name = "vreg_l2a_2p3"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name = "vreg_l3a_1p2"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name = "vreg_l5a_0p8"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name = "vreg_l6a_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <888000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name = "vreg_l9a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name = "vreg_l10a_2p95"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name = "vreg_l11a_0p91"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name = "vreg_l16a_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name = "vreg_l17a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name = "vreg_l18a_1p2"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; +}; + +&qup_i2c1_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c2_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c3_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c4_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c5_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c6_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c9_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c10_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c11_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c12_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c13_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c14_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c15_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_spi1_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi1_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi2_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi2_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi3_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi3_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi4_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi4_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi5_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi5_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi6_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi6_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi9_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi9_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi10_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi10_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi11_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi11_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi12_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi12_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi14_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi14_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi15_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi15_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_uart7_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_tx { + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi new file mode 100644 index 000000000000..f234159d2060 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -0,0 +1,1333 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/clock/qcom,qdu1000-gcc.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen: chosen { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_OFF: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <274>; + exit-latency-us = <480>; + min-residency-us = <3934>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + entry-latency-us = <584>; + exit-latency-us = <2332>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x41000044>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + entry-latency-us = <2893>; + exit-latency-us = <4023>; + min-residency-us = <9987>; + arm,psci-suspend-param = <0x41003344>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-qdu1000", "qcom,scm"; + }; + }; + + mc_virt: interconnect-0 { + compatible = "qcom,qdu1000-mc-virt"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + clk_virt: interconnect-1 { + compatible = "qcom,qdu1000-clk-virt"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_dt_log_mem: xbl-dt-log@80600000 { + reg = <0x0 0x80600000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump@80640000 { + reg = <0x0 0x80640000 0x0 0x1c0000>; + no-map; + }; + + aop_image_mem: aop-image@80800000 { + reg = <0x0 0x80800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config@80880000 { + reg = <0x0 0x80880000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump@808a0000 { + reg = <0x0 0x808a0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log@808e0000 { + reg = <0x0 0x808e0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log@808e4000 { + reg = <0x0 0x808e4000 0x0 0x10000>; + no-map; + }; + + smem_mem: smem@80900000 { + compatible = "qcom,smem"; + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: cpucp-fw@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + xbl_sc_mem: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0x40000>; + no-map; + }; + + tz_stat_mem: tz-stat@81d00000 { + reg = <0x0 0x81d00000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@81e00000 { + reg = <0x0 0x81e00000 0x0 0x500000>; + no-map; + }; + + qtee_mem: qtee@82300000 { + reg = <0x0 0x82300000 0x0 0x500000>; + no-map; + }; + + ta_mem: ta@82800000 { + reg = <0x0 0x82800000 0x0 0xa00000>; + no-map; + }; + + fs1_mem: fs1@83200000 { + reg = <0x0 0x83200000 0x0 0x400000>; + no-map; + }; + + fs2_mem: fs2@83600000 { + reg = <0x0 0x83600000 0x0 0x400000>; + no-map; + }; + + fs3_mem: fs3@83a00000 { + reg = <0x0 0x83a00000 0x0 0x400000>; + no-map; + }; + + /* Linux kernel image is loaded at 0x83e00000 */ + + ipa_fw_mem: ipa-fw@8be00000 { + reg = <0x0 0x8be00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8be10000 { + reg = <0x0 0x8be10000 0x0 0x14000>; + no-map; + }; + + mpss_mem: mpss@8c000000 { + reg = <0x0 0x8c000000 0x0 0x12c00000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 { + reg = <0x0 0x9ec00000 0x0 0x80000>; + no-map; + }; + + tenx_mem: tenx@a0000000 { + reg = <0x0 0xa0000000 0x0 0x19600000>; + no-map; + }; + + oem_tenx_mem: oem-tenx@b9600000 { + reg = <0x0 0xb9600000 0x0 0x6a00000>; + no-map; + }; + + tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 { + reg = <0x0 0xc0000000 0x0 0x3200000>; + no-map; + }; + + ipa_buffer_mem: ipa-buffer@c3200000 { + reg = <0x0 0xc3200000 0x0 0x12c00000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@80000 { + compatible = "qcom,qdu1000-gcc"; + reg = <0x0 0x80000 0x0 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpi_dma0: dma-controller@900000 { + compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x900000 0x0 0x60000>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0xf6 0x0>; + #dma-cells = <3>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 + &clk_virt SLAVE_QUP_CORE_0 0>; + interconnect-names = "qup-core"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x98c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x990000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x994000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x998000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart7: serial@99c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x99c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0xa00000 0x0 0x60000>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x116 0x0>; + #dma-cells = <3>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x103 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart8_default>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa90000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa94000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart13: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa94000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart13_default>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa98000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa98000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa9c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa9c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + system_noc: interconnect@1640000 { + compatible = "qcom,qdu1000-system-noc"; + reg = <0x0 0x1640000 0x0 0x45080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,qdu1000-pdc", "qcom,pdc"; + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0xc400000 0x0 0x3000>, + <0x0 0xc500000 0x0 0x400000>, + <0x0 0xc440000 0x0 0x80000>, + <0x0 0xc4c0000 0x0 0x10000>, + <0x0 0xc42d000 0x0 0x4000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,qdu1000-tlmm"; + reg = <0x0 0xf000000 0x0 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup00"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins = "gpio10", "gpio11"; + function = "qup01"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + pins = "gpio10", "gpio11", "gpio12"; + function = "qup01"; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio13"; + function = "gpio"; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins = "gpio12", "gpio13"; + function = "qup02"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + pins = "gpio12", "gpio13", "gpio10"; + function = "qup02"; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio11"; + function = "gpio"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins = "gpio14", "gpio15"; + function = "qup03"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + pins = "gpio14", "gpio15", "gpio16"; + function = "qup03"; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio17"; + function = "gpio"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins = "gpio16", "gpio17"; + function = "qup04"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + pins = "gpio16", "gpio17", "gpio14"; + function = "qup04"; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio15"; + function = "gpio"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + pins = "gpio130", "gpio131"; + function = "qup05"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + pins = "gpio130", "gpio131", "gpio132"; + function = "qup05"; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio133"; + function = "gpio"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + pins = "gpio132", "gpio133"; + function = "qup06"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + pins = "gpio132", "gpio133", "gpio130"; + function = "qup06"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio131"; + function = "gpio"; + }; + + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio135"; + function = "qup07"; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio134"; + function = "qup07"; + }; + + qup_uart8_default: qup-uart8-default-state { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "qup10"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + pins = "gpio22", "gpio23"; + function = "qup11"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + pins = "gpio22", "gpio23", "gpio24"; + function = "qup11"; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio25"; + function = "gpio"; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + pins = "gpio24", "gpio25"; + function = "qup12"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + pins = "gpio24", "gpio25", "gpio22"; + function = "qup12"; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio23"; + function = "gpio"; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + pins = "gpio26", "gpio27"; + function = "qup13"; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio26", "gpio27", "gpio28"; + function = "qup13"; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio29"; + function = "gpio"; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + pins = "gpio28", "gpio29"; + function = "qup14"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + pins = "gpio28", "gpio29", "gpio26"; + function = "qup14"; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio27"; + function = "gpio"; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + pins = "gpio30", "gpio31"; + function = "qup15"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + pins = "gpio30", "gpio31", "gpio32"; + function = "qup15"; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio33"; + function = "gpio"; + }; + + qup_uart13_default: qup-uart13-default-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "qup15"; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + pins = "gpio34", "gpio35"; + function = "qup16"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + pins = "gpio34", "gpio35", "gpio36"; + function = "qup16"; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio37", "gpio38"; + function = "gpio"; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + pins = "gpio40", "gpio41"; + function = "qup17"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + pins = "gpio40", "gpio41", "gpio30"; + function = "qup17"; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio31"; + function = "gpio"; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <0>; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <1>; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>, + <0x17426000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <2>; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <3>; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <4>; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <5>; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, + <WAKE_TCS 3>, <CONTROL_TCS 0>; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,qdu1000-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,qdu1000-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d90000 { + compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <1>; + }; + + gem_noc: interconnect@19100000 { + compatible = "qcom,qdu1000-gem-noc"; + reg = <0x0 0x19100000 0x0 0xB8080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 8c64cb060e21..aa0a7bd7307c 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -238,7 +238,7 @@ }; &apps_rsc { - pm8009-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8009-1-rpmh-regulators"; qcom,pmic-id = "f"; @@ -284,7 +284,7 @@ }; }; - pm8150-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -417,7 +417,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -1007,6 +1007,8 @@ }; &swr0 { + status = "okay"; + left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; @@ -1322,6 +1324,10 @@ status = "okay"; }; +&wsamacro { + status = "okay"; +}; + /* PINCTRL - additions to nodes defined in sm8250.dtsi */ &qup_spi0_cs_gpio { drive-strength = <6>; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts new file mode 100644 index 000000000000..2cc893ae4d10 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "qru1000.dtsi" +#include "pm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QRU1000 IDP"; + compatible = "qcom,qru1000-idp", "qcom,qru1000"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; +}; + +&apps_rsc { + regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vph_pwr>; + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; + vdd-l6-l9-supply = <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply = <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name = "vreg_s2a_0p5"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name = "vreg_s3a_1p05"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name = "vreg_s6a_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name = "vreg_s7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name = "vreg_s8a_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name = "vreg_l1a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name = "vreg_l2a_2p3"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name = "vreg_l3a_1p2"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name = "vreg_l5a_0p8"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name = "vreg_l6a_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <888000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name = "vreg_l9a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name = "vreg_l10a_2p95"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name = "vreg_l11a_0p91"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name = "vreg_l16a_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name = "vreg_l17a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name = "vreg_l18a_1p2"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; +}; + +&qup_i2c1_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c2_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c3_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c4_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c5_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c6_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c9_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c10_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c11_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c12_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c13_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c14_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c15_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_spi1_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi1_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi2_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi2_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi3_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi3_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi4_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi4_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi5_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi5_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi6_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi6_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi9_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi9_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi10_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi10_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi11_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi11_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi12_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi12_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi14_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi14_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi15_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi15_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_uart7_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_tx { + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi new file mode 100644 index 000000000000..eac5dc54a8ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "qdu1000.dtsi" +/delete-node/ &tenx_mem; +/delete-node/ &oem_tenx_mem; +/delete-node/ &tenx_q6_buffer_mem; + +&reserved_memory { + oem_tenx_mem: oem-tenx@a0000000 { + reg = <0x0 0xa0000000 0x0 0x6400000>; + no-map; + }; + + mpss_diag_buffer_mem: mpss-diag-buffer@aea00000 { + reg = <0x0 0xaea00000 0x0 0x6400000>; + no-map; + }; + + tenx_q6_buffer_mem: tenx-q6-buffer@b4e00000 { + reg = <0x0 0xb4e00000 0x0 0x3200000>; + no-map; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index eafdfbbf40b9..459384ec8f23 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -72,7 +72,7 @@ }; &apps_rsc { - pmm8155au-1-rpmh-regulators { + regulators-0 { compatible = "qcom,pmm8155au-rpmh-regulators"; qcom,pmic-id = "a"; @@ -201,7 +201,7 @@ }; }; - pmm8155au-2-rpmh-regulators { + regulators-1 { compatible = "qcom,pmm8155au-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index bb4270e8f551..fd253942e5e5 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -111,7 +111,7 @@ }; &apps_rsc { - pmm8540-a-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -151,7 +151,7 @@ }; }; - pmm8540-c-regulators { + regulators-1 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "c"; @@ -224,7 +224,7 @@ }; }; - pmm8540-g-regulators { + regulators-2 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "g"; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index eacc1764255b..3ccb5ffdb3ca 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -317,27 +317,31 @@ &tlmm { i2c0_default: i2c0-default-state { + /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ pins = "gpio135", "gpio136"; - function = "qup15"; + function = "qup0"; drive-strength = <2>; bias-pull-up; }; i2c1_default: i2c1-default-state { + /* To PM40028B-F3EI PCIe switch */ pins = "gpio158", "gpio159"; - function = "qup15"; + function = "qup1"; drive-strength = <2>; bias-pull-up; }; i2c12_default: i2c12-default-state { + /* To Maxim max20411 */ pins = "gpio0", "gpio1"; - function = "qup15"; + function = "qup12"; drive-strength = <2>; bias-pull-up; }; i2c15_default: i2c15-default-state { + /* To display connector (SIP1 only) */ pins = "gpio36", "gpio37"; function = "qup15"; drive-strength = <2>; @@ -345,6 +349,7 @@ }; i2c18_default: i2c18-default-state { + /* To ASM330LHH IMU (SIP1 only) */ pins = "gpio66", "gpio67"; function = "qup18"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 774f9d45f051..c3bdd3295c02 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -90,7 +90,7 @@ }; &apps_rsc { - pm6150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm6150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -212,7 +212,7 @@ }; }; - pm6150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm6150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -430,7 +430,7 @@ pinctrl-names = "default", "sleep"; pinctrl-1 = <&qup_uart3_sleep>; - bluetooth: wcn3990-bt { + bluetooth: bluetooth { compatible = "qcom,wcn3990-bt"; vddio-supply = <&vreg_l10a_1p8>; vddxo-supply = <&vreg_l1c_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index dcb179b2a3fb..423630c4d02c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -438,7 +438,7 @@ }; &apps_rsc { - pm6150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm6150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -551,7 +551,7 @@ }; }; - pm6150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm6150l-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi index ae2552094cda..020ef666e35f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi @@ -32,12 +32,8 @@ "TX SWR_DMIC6", "DMIC7_OUTPUT", "TX SWR_DMIC7", "DMIC8_OUTPUT"; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - #address-cells = <1>; #size-cells = <0>; - #sound-dai-cells = <0>; dai-link@0 { link-name = "MAX98360A"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd-pro.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd-pro.dts new file mode 100644 index 000000000000..4ee5f0b0a5de --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd-pro.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 CRD 3+ Pro board device tree source + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sc7280-herobrine-crd.dts" +#include "sc7280-herobrine-pro-sku.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 CRD Pro platform (rev5+)"; + compatible = "google,zoglin-sku1536", "google,hoglin-sku1536", "qcom,sc7280"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi index 3d639c70a06e..0add7a2a099c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi @@ -55,6 +55,7 @@ ts_i2c: &i2c13 { reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; vdd-supply = <&ts_avdd>; + mainboard-vddio-supply = <&ts_avccio>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-pro-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-pro-sku.dtsi new file mode 100644 index 000000000000..fb4bbe8aeda0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-pro-sku.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Google Herobrine dts fragment for PRO SKUs + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/delete-node/ &vreg_s9c_0p676; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 17553e0fd6fd..818d4046d2c7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -55,6 +55,7 @@ ts_i2c: &i2c13 { reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; vcc33-supply = <&ts_avdd>; + vccio-supply = <&ts_avccio>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index d21f73bf0873..b6137816f2f3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -108,6 +108,24 @@ pinctrl-names = "default"; pinctrl-0 = <&en_pp3300_dx_edp>; + regulator-enable-ramp-delay = <3000>; + + /* + * eDP panel specs nearly always have a spec that says you + * shouldn't turn them off an on again without waiting 500ms. + * Add this as a board constraint since this rail is shared + * between the panel and touchscreen. + */ + off-on-delay-us = <500000>; + + /* + * Stat the regulator on. This has the advantage of starting + * the slow process of powering the panel on as soon as we + * probe the regulator. It also avoids tripping the + * off-on-delay immediately on every bootup. + */ + regulator-boot-on; + vin-supply = <&pp3300_z1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 43e61a1aa779..8b5293e7fd2a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -113,12 +113,8 @@ "TX SWR_DMIC6", "DMIC7_OUTPUT", "TX SWR_DMIC7", "DMIC8_OUTPUT"; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - #address-cells = <1>; #size-cells = <0>; - #sound-dai-cells = <0>; dai-link@0 { link-name = "MAX98360A"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index cd6ee84b36fd..88204f794ccb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -230,9 +230,15 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + /* + * The initial design of this regulator was to use it as 3.3V, + * but due to later changes in design it was changed to 1.8V. + * The original name is kept due to same schematic. + */ + ts_avccio: vreg_l3c_3p0: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3540000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 20c629172477..2179c06b4e3b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -142,7 +142,7 @@ }; &apps_rsc { - pmc8280-1-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -179,7 +179,7 @@ }; }; - pmc8280c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -208,7 +208,7 @@ }; }; - pmc8280-2-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "d"; @@ -264,6 +264,7 @@ &mdss0_dp3 { compatible = "qcom,sc8280xp-edp"; + /delete-property/ #sound-dai-cells; data-lanes = <0 1 2 3>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index f936b020a71d..654b6b310bc9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -241,7 +241,7 @@ }; &apps_rsc { - pmc8280-1-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -292,7 +292,7 @@ }; }; - pmc8280c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; vdd-bob-supply = <&vreg_vph_pwr>; @@ -326,7 +326,7 @@ }; }; - pmc8280-2-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "d"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index fa2d0d7d1367..52172f79f2f2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2646,7 +2646,7 @@ <0 0x3550000 0x0 0x10000>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&lpass_tlmm 0 0 18>; + gpio-ranges = <&lpass_tlmm 0 0 19>; clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; @@ -3204,7 +3204,8 @@ reg = <0 0xae9a000 0 0x200>, <0 0xae9a200 0 0x200>, <0 0xae9a400 0 0x600>, - <0 0xae9b000 0 0x400>; + <0 0xae9b000 0 0x400>, + <0 0xae9b400 0 0x400>; clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, @@ -3275,7 +3276,8 @@ reg = <0 0xaea0000 0 0x200>, <0 0xaea0200 0 0x200>, <0 0xaea0400 0 0x600>, - <0 0xaea1000 0 0x400>; + <0 0xaea1000 0 0x400>, + <0 0xaea1400 0 0x400>; clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, @@ -4150,7 +4152,8 @@ reg = <0 0x22090000 0 0x200>, <0 0x22090200 0 0x200>, <0 0x22090400 0 0x600>, - <0 0x22091000 0 0x400>; + <0 0x22091000 0 0x400>, + <0 0x22091400 0 0x400>; clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, @@ -4222,7 +4225,8 @@ reg = <0 0x22098000 0 0x200>, <0 0x22098200 0 0x200>, <0 0x22098400 0 0x600>, - <0 0x22099000 0 0x400>; + <0 0x22099000 0 0x400>, + <0 0x22099400 0 0x400>; clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, @@ -4293,7 +4297,8 @@ reg = <0 0x2209a000 0 0x200>, <0 0x2209a200 0 0x200>, <0 0x2209a400 0 0x600>, - <0 0x2209b000 0 0x400>; + <0 0x2209b000 0 0x400>, + <0 0x2209b400 0 0x400>; clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, @@ -4364,7 +4369,8 @@ reg = <0 0x220a0000 0 0x200>, <0 0x220a0200 0 0x200>, <0 0x220a0400 0 0x600>, - <0 0x220a1000 0 0x400>; + <0 0x220a1000 0 0x400>, + <0 0x220a1400 0 0x400>; clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index ec9946e5f08d..02f14692dd9d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -788,6 +788,55 @@ }; }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm670-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@14e0000 { + compatible = "qcom,sdm670-dc-noc"; + reg = <0 0x014e0000 0 0x400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sdm670-config-noc"; + reg = <0 0x01500000 0 0x5080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdm670-system-noc"; + reg = <0 0x01620000 0 0x18080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sdm670-aggre1-noc"; + reg = <0 0x016e0000 0 0x15080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sdm670-aggre2-noc"; + reg = <0 0x01700000 0 0x1f300>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm670-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tlmm: pinctrl@3400000 { compatible = "qcom,sdm670-tlmm"; reg = <0 0x03400000 0 0xc00000>; @@ -1083,6 +1132,13 @@ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; }; + gladiator_noc: interconnect@17900000 { + compatible = "qcom,sdm670-gladiator-noc"; + reg = <0 0x17900000 0 0xd080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + apps_rsc: rsc@179c0000 { compatible = "qcom,rpmh-rsc"; reg = <0 0x179c0000 0 0x10000>, diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index a78075155310..f2b48241d15c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -339,7 +339,7 @@ &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -621,7 +621,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -862,7 +862,7 @@ ap_ts_i2c: &i2c14 { pinctrl-0 = <&qup_uart6_4pin>; - bluetooth: wcn3990-bt { + bluetooth: bluetooth { compatible = "qcom,wcn3990-bt"; vddio-supply = <&src_pp1800_s4a>; vddxo-supply = <&pp1800_l7a_wcn3990>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 6b355589edb3..d4866feef2c4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -11,6 +11,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" @@ -269,7 +270,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; vdd-s1-supply = <&vph_pwr>; @@ -394,7 +395,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -702,7 +703,7 @@ }; &sound { - compatible = "qcom,db845c-sndcard"; + compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active @@ -970,15 +971,6 @@ function = "gpio"; bias-pull-up; }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart3 { @@ -1084,10 +1076,6 @@ }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 36f291d4d691..f942c5afea9b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -166,7 +166,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -419,7 +419,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -433,7 +433,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 482f43fe0151..d1440b790fa6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -117,7 +117,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -382,7 +382,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -396,7 +396,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 548e34632de2..64638ea94db7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -9,8 +9,11 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" @@ -145,7 +148,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -281,7 +284,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -295,7 +298,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -466,6 +469,44 @@ status = "okay"; }; +&q6afedai { + qi2s@22 { + reg = <22>; + qcom,sd-lines = <1>; + }; + + qi2s@23 { + reg = <23>; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; + + dai@3 { + reg = <3>; + }; + + dai@4 { + reg = <4>; + }; + + dai@5 { + reg = <5>; + }; +}; + &qupv3_id_1 { status = "okay"; }; @@ -494,6 +535,141 @@ bias-disable; }; +&sound { + compatible = "qcom,sdm845-sndcard"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-names = "default"; + status = "okay"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + mm4-dai-link { + link-name = "MultiMedia4"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>; + }; + }; + + mm5-dai-link { + link-name = "MultiMedia5"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA5>; + }; + }; + + mm6-dai-link { + link-name = "MultiMedia6"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA6>; + }; + }; + + speaker_playback_dai: speaker-dai-link { + link-name = "Speaker Playback"; + cpu { + sound-dai = <&q6afedai QUATERNARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback 1"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 0>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture 1"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 1>; + }; + }; + + slim2-dai-link { + link-name = "SLIM Playback 2"; + cpu { + sound-dai = <&q6afedai SLIMBUS_1_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 2>; /* AIF2_PB */ + }; + }; + + slimcap2-dai-link { + link-name = "SLIM Capture 2"; + cpu { + sound-dai = <&q6afedai SLIMBUS_1_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 3>; /* AIF2_CAP */ + }; + }; + + slimcap3-dai-link { + link-name = "SLIM Capture 3"; + cpu { + sound-dai = <&q6afedai SLIMBUS_2_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 5>; /* AIF3_CAP */ + }; + }; +}; + &uart6 { status = "okay"; @@ -613,6 +789,16 @@ bias-pull-down; input-enable; }; + + speaker_default: speaker-default-state { + mux { + pins = "gpio69"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + output-high; + }; + }; }; &venus { @@ -620,6 +806,17 @@ firmware-name = "qcom/sdm845/oneplus6/venus.mbn"; }; +&wcd9340 { + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; +}; + &wifi { status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index bf2cf92e8976..6cdda971bb4b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -32,3 +32,43 @@ &bq27441_fg { monitored-battery = <&battery>; }; + +&i2c4 { + status = "okay"; + + max98927_codec: max98927@3a { + compatible = "maxim,max98927"; + reg = <0x3a>; + #sound-dai-cells = <1>; + + pinctrl-0 = <&speaker_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; + + vmon-slot-no = <1>; + imon-slot-no = <0>; + }; +}; + +&sound { + model = "OnePlus 6"; + audio-routing = "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS4", + "AMIC4", "MIC BIAS1", + "AMIC5", "MIC BIAS4"; +}; + +&speaker_playback_dai { + codec { + sound-dai = <&max98927_codec 0>; + }; +}; + +&wcd9340 { + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <2700000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 1b6b5bf368df..086d14e2de92 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -29,10 +29,39 @@ compatible = "samsung,s6e3fc2x01"; }; +&i2c4 { + /* nxp,tfa9894 @ 0x34 */ +}; + &bq27441_fg { monitored-battery = <&battery>; }; +&sound { + model = "OnePlus 6T"; + audio-routing = "RX_BIAS", "MCLK", + "AMIC1", "MIC BIAS3", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS4", + "AMIC4", "MIC BIAS1", + "AMIC5", "MIC BIAS3"; + +}; + +/* + * The TFA9894 codec is currently unsupported. + * We need to delete the node to allow the soundcard + * to probe for headphones/earpiece. + */ +/delete-node/ &speaker_playback_dai; + &rmi4_f12 { touchscreen-y-mm = <148>; }; + +&wcd9340 { + qcom,micbias1-microvolt = <2700000>; + qcom,micbias2-microvolt = <2700000>; + qcom,micbias3-microvolt = <2700000>; + qcom,micbias4-microvolt = <2700000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index e742c27fe91f..d37a433130b9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -73,7 +73,7 @@ &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -332,7 +332,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 5d0509f61fe8..b54e304abf71 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -111,7 +111,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -376,7 +376,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -390,7 +390,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 85ff0a0789ea..4984c7496c31 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -99,7 +99,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -329,7 +329,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -340,7 +340,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi b/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi new file mode 100644 index 000000000000..0d7c37f39176 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 SoC device tree source + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +&slim { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + wcd9340_ifd: ifd@0,0 { + compatible = "slim217,250"; + reg = <0 0>; + }; + + wcd9340: codec@1,0 { + compatible = "slim217,250"; + reg = <1 0>; + slim-ifc-dev = <&wcd9340_ifd>; + + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + + #address-cells = <1>; + #size-cells = <1>; + + wcdgpio: gpio-controller@42 { + compatible = "qcom,wcd9340-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42 0x2>; + }; + + swm: swm@c85 { + compatible = "qcom,soundwire-v1.3.0"; + reg = <0xc85 0x40>; + interrupts-extended = <&wcd9340 20>; + + qcom,dout-ports = <6>; + qcom,din-ports = <2>; + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>; + + #sound-dai-cells = <1>; + clocks = <&wcd9340>; + clock-names = "iface"; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + }; +}; + +&tlmm { + wcd_intr_default: wcd-intr-default-state { + pins = "gpio54"; + function = "gpio"; + + input-enable; + bias-pull-down; + drive-strength = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 31ec5ff0a63d..e0fda4d754fe 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" @@ -97,6 +98,12 @@ no-map; }; + /* Cont splash region set up by the bootloader */ + cont_splash_mem: framebuffer@9d400000 { + reg = <0 0x9d400000 0 0x2400000>; + no-map; + }; + rmtfs_mem: memory@f6301000 { compatible = "qcom,rmtfs-mem"; reg = <0 0xf6301000 0 0x200000>; @@ -123,7 +130,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -375,7 +382,7 @@ }; &sound { - compatible = "qcom,db845c-sndcard"; + compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active>; pinctrl-names = "default"; @@ -466,15 +473,6 @@ function = "gpio"; bias-pull-up; }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart6 { @@ -543,10 +541,6 @@ }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 8b42efbf1996..1b7fdbae6a2b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -13,6 +13,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" #include "pm8005.dtsi" @@ -143,7 +144,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -343,7 +344,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -355,7 +356,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -616,14 +617,6 @@ drive-strength = <2>; bias-pull-down; }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart6 { @@ -700,10 +693,6 @@ }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 9ffc0fe07c21..479859bd8ab3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3841,65 +3841,7 @@ iommus = <&apps_smmu 0x1806 0x0>; #address-cells = <1>; #size-cells = <0>; - - slim@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - - wcd9340_ifd: ifd@0,0 { - compatible = "slim217,250"; - reg = <0 0>; - }; - - wcd9340: codec@1,0 { - compatible = "slim217,250"; - reg = <1 0>; - slim-ifc-dev = <&wcd9340_ifd>; - - #sound-dai-cells = <1>; - - interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "mclk"; - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - - #address-cells = <1>; - #size-cells = <1>; - - wcdgpio: gpio-controller@42 { - compatible = "qcom,wcd9340-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x42 0x2>; - }; - - swm: swm@c85 { - compatible = "qcom,soundwire-v1.3.0"; - reg = <0xc85 0x40>; - interrupts-extended = <&wcd9340 20>; - - qcom,dout-ports = <6>; - qcom,din-ports = <2>; - qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>; - qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>; - - #sound-dai-cells = <1>; - clocks = <&wcd9340>; - clock-names = "iface"; - #address-cells = <2>; - #size-cells = <0>; - }; - }; - }; + status = "disabled"; }; lmh_cluster1: lmh@17d70800 { diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 7038a0f7c06e..67d2a663ce75 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -13,6 +13,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm850.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" /* @@ -99,7 +100,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -512,7 +513,7 @@ }; &sound { - compatible = "qcom,db845c-sndcard"; + compatible = "lenovo,yoga-c630-sndcard", "qcom,sdm845-sndcard"; model = "Lenovo-YOGA-C630-13Q50"; audio-routing = @@ -628,15 +629,6 @@ drive-strength = <2>; }; - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; - lid_pin_active: lid-pin-state { pins = "gpio124"; function = "gpio"; @@ -747,10 +739,6 @@ }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 6e361fe184f5..9850140514ba 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -14,6 +14,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm850.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" /* @@ -129,7 +130,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -552,15 +553,6 @@ */ output-high; }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart6 { @@ -656,10 +648,6 @@ }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 50cb8a82ecd5..4d6ec815b78b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -345,25 +345,100 @@ }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 30>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; tcsr_mutex: hwlock@340000 { compatible = "qcom,tcsr-mutex"; - reg = <0x00340000 0x20000>; + reg = <0x0 0x00340000 0x0 0x20000>; #hwlock-cells = <1>; }; tlmm: pinctrl@500000 { compatible = "qcom,sm6115-tlmm"; - reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; + reg = <0x0 0x00500000 0x0 0x400000>, + <0x0 0x00900000 0x0 0x400000>, + <0x0 0x00d00000 0x0 0x400000>; reg-names = "west", "south", "east"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; - gpio-ranges = <&tlmm 0 0 121>; + gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -559,7 +634,7 @@ gcc: clock-controller@1400000 { compatible = "qcom,gcc-sm6115"; - reg = <0x01400000 0x1f0000>; + reg = <0x0 0x01400000 0x0 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; #clock-cells = <1>; @@ -569,7 +644,7 @@ usb_1_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; - reg = <0x01613000 0x180>; + reg = <0x0 0x01613000 0x0 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; @@ -583,7 +658,7 @@ qfprom@1b40000 { compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; - reg = <0x01b40000 0x7000>; + reg = <0x0 0x01b40000 0x0 0x7000>; #address-cells = <1>; #size-cells = <1>; @@ -595,18 +670,18 @@ rng: rng@1b53000 { compatible = "qcom,prng-ee"; - reg = <0x01b53000 0x1000>; + reg = <0x0 0x01b53000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x01c40000 0x1100>, - <0x01e00000 0x2000000>, - <0x03e00000 0x100000>, - <0x03f00000 0xa0000>, - <0x01c0a000 0x26000>; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; @@ -620,8 +695,8 @@ tsens0: thermal-sensor@4410000 { compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; - reg = <0x04411000 0x1ff>, /* TM */ - <0x04410000 0x8>; /* SROT */ + reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ + <0x0 0x04410000 0x0 0x8>; /* SROT */ #qcom,sensors = <16>; interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; @@ -631,17 +706,19 @@ rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; - reg = <0x045f0000 0x7000>; + reg = <0x0 0x045f0000 0x0 0x7000>; }; sram@4690000 { compatible = "qcom,rpm-stats"; - reg = <0x04690000 0x10000>; + reg = <0x0 0x04690000 0x0 0x10000>; }; sdhc_1: mmc@4744000 { compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>, + <0x0 0x04748000 0x0 0x8000>; reg-names = "hc", "cqhci", "ice"; interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, @@ -664,7 +741,7 @@ sdhc_2: mmc@4784000 { compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x04784000 0x1000>; + reg = <0x0 0x04784000 0x0 0x1000>; reg-names = "hc"; interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, @@ -707,7 +784,7 @@ ufs_mem_hc: ufs@4804000 { compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; reg-names = "std", "ice"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; @@ -751,9 +828,9 @@ ufs_mem_phy: phy@4807000 { compatible = "qcom,sm6115-qmp-ufs-phy"; - reg = <0x04807000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x0 0x04807000 0x0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; @@ -764,16 +841,16 @@ status = "disabled"; ufs_mem_phy_lanes: phy@4807400 { - reg = <0x04807400 0x098>, - <0x04807600 0x130>, - <0x04807c00 0x16c>; + reg = <0x0 0x04807400 0x0 0x098>, + <0x0 0x04807600 0x0 0x130>, + <0x0 0x04807c00 0x0 0x16c>; #phy-cells = <0>; }; }; gpi_dma0: dma-controller@4a00000 { compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; - reg = <0x04a00000 0x60000>; + reg = <0x0 0x04a00000 0x0 0x60000>; interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, @@ -793,19 +870,19 @@ qupv3_id_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0x04ac0000 0x2000>; + reg = <0x0 0x04ac0000 0x0 0x2000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; iommus = <&apps_smmu 0xe3 0x0>; ranges; status = "disabled"; i2c0: i2c@4a80000 { compatible = "qcom,geni-i2c"; - reg = <0x04a80000 0x4000>; + reg = <0x0 0x04a80000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; @@ -821,7 +898,7 @@ spi0: spi@4a80000 { compatible = "qcom,geni-spi"; - reg = <0x04a80000 0x4000>; + reg = <0x0 0x04a80000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; @@ -837,7 +914,7 @@ i2c1: i2c@4a84000 { compatible = "qcom,geni-i2c"; - reg = <0x04a84000 0x4000>; + reg = <0x0 0x04a84000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; @@ -853,7 +930,7 @@ spi1: spi@4a84000 { compatible = "qcom,geni-spi"; - reg = <0x04a84000 0x4000>; + reg = <0x0 0x04a84000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; @@ -869,7 +946,7 @@ i2c2: i2c@4a88000 { compatible = "qcom,geni-i2c"; - reg = <0x04a88000 0x4000>; + reg = <0x0 0x04a88000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; @@ -885,7 +962,7 @@ spi2: spi@4a88000 { compatible = "qcom,geni-spi"; - reg = <0x04a88000 0x4000>; + reg = <0x0 0x04a88000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; @@ -901,7 +978,7 @@ i2c3: i2c@4a8c000 { compatible = "qcom,geni-i2c"; - reg = <0x04a8c000 0x4000>; + reg = <0x0 0x04a8c000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; @@ -917,7 +994,7 @@ spi3: spi@4a8c000 { compatible = "qcom,geni-spi"; - reg = <0x04a8c000 0x4000>; + reg = <0x0 0x04a8c000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; @@ -933,7 +1010,7 @@ i2c4: i2c@4a90000 { compatible = "qcom,geni-i2c"; - reg = <0x04a90000 0x4000>; + reg = <0x0 0x04a90000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; @@ -949,7 +1026,7 @@ spi4: spi@4a90000 { compatible = "qcom,geni-spi"; - reg = <0x04a90000 0x4000>; + reg = <0x0 0x04a90000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; @@ -963,9 +1040,18 @@ status = "disabled"; }; + uart4: serial@4a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2c5: i2c@4a94000 { compatible = "qcom,geni-i2c"; - reg = <0x04a94000 0x4000>; + reg = <0x0 0x04a94000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; @@ -981,7 +1067,7 @@ spi5: spi@4a94000 { compatible = "qcom,geni-spi"; - reg = <0x04a94000 0x4000>; + reg = <0x0 0x04a94000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; @@ -992,15 +1078,14 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; }; }; usb_1: usb@4ef8800 { compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; - reg = <0x04ef8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x0 0x04ef8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, @@ -1026,7 +1111,7 @@ usb_1_dwc3: usb@4e00000 { compatible = "snps,dwc3"; - reg = <0x04e00000 0xcd00>; + reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb_1_hsphy>; phy-names = "usb2-phy"; @@ -1043,7 +1128,7 @@ mdss: display-subsystem@5e00000 { compatible = "qcom,sm6115-mdss"; - reg = <0x05e00000 0x1000>; + reg = <0x0 0x05e00000 0x0 0x1000>; reg-names = "mdss"; power-domains = <&dispcc MDSS_GDSC>; @@ -1059,16 +1144,16 @@ iommus = <&apps_smmu 0x420 0x2>, <&apps_smmu 0x421 0x0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; status = "disabled"; mdp: display-controller@5e01000 { compatible = "qcom,sm6115-dpu"; - reg = <0x05e01000 0x8f000>, - <0x05eb0000 0x2008>; + reg = <0x0 0x05e01000 0x0 0x8f000>, + <0x0 0x05eb0000 0x0 0x2008>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, @@ -1097,7 +1182,7 @@ port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; }; @@ -1132,9 +1217,9 @@ }; }; - dsi0: dsi@5e94000 { + mdss_dsi0: dsi@5e94000 { compatible = "qcom,dsi-ctrl-6g-qcm2290"; - reg = <0x05e94000 0x400>; + reg = <0x0 0x05e94000 0x0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -1155,11 +1240,11 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmpd SM6115_VDDCX>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; #address-cells = <1>; #size-cells = <0>; @@ -1172,14 +1257,14 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; @@ -1204,11 +1289,11 @@ }; }; - dsi0_phy: phy@5e94400 { + mdss_dsi0_phy: phy@5e94400 { compatible = "qcom,dsi-phy-14nm-2290"; - reg = <0x05e94400 0x100>, - <0x05e94500 0x300>, - <0x05e94800 0x188>; + reg = <0x0 0x05e94400 0x0 0x100>, + <0x0 0x05e94500 0x0 0x300>, + <0x0 0x05e94800 0x0 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -1226,11 +1311,11 @@ dispcc: clock-controller@5f00000 { compatible = "qcom,sm6115-dispcc"; - reg = <0x05f00000 0x20000>; + reg = <0x0 0x05f00000 0 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; #clock-cells = <1>; #reset-cells = <1>; @@ -1239,8 +1324,8 @@ stm@8002000 { compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x08002000 0x1000>, - <0x0e280000 0x180000>; + reg = <0x0 0x08002000 0x0 0x1000>, + <0x0 0x0e280000 0x0 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; @@ -1259,7 +1344,7 @@ cti0: cti@8010000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08010000 0x1000>; + reg = <0x0 0x08010000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1269,7 +1354,7 @@ cti1: cti@8011000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08011000 0x1000>; + reg = <0x0 0x08011000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1279,7 +1364,7 @@ cti2: cti@8012000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08012000 0x1000>; + reg = <0x0 0x08012000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1289,7 +1374,7 @@ cti3: cti@8013000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08013000 0x1000>; + reg = <0x0 0x08013000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1299,7 +1384,7 @@ cti4: cti@8014000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08014000 0x1000>; + reg = <0x0 0x08014000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1309,7 +1394,7 @@ cti5: cti@8015000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08015000 0x1000>; + reg = <0x0 0x08015000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1319,7 +1404,7 @@ cti6: cti@8016000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08016000 0x1000>; + reg = <0x0 0x08016000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1329,7 +1414,7 @@ cti7: cti@8017000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08017000 0x1000>; + reg = <0x0 0x08017000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1339,7 +1424,7 @@ cti8: cti@8018000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08018000 0x1000>; + reg = <0x0 0x08018000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1349,7 +1434,7 @@ cti9: cti@8019000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x08019000 0x1000>; + reg = <0x0 0x08019000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1359,7 +1444,7 @@ cti10: cti@801a000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0801a000 0x1000>; + reg = <0x0 0x0801a000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1369,7 +1454,7 @@ cti11: cti@801b000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0801b000 0x1000>; + reg = <0x0 0x0801b000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1379,7 +1464,7 @@ cti12: cti@801c000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0801c000 0x1000>; + reg = <0x0 0x0801c000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1389,7 +1474,7 @@ cti13: cti@801d000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0801d000 0x1000>; + reg = <0x0 0x0801d000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1399,7 +1484,7 @@ cti14: cti@801e000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0801e000 0x1000>; + reg = <0x0 0x0801e000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1409,7 +1494,7 @@ cti15: cti@801f000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0801f000 0x1000>; + reg = <0x0 0x0801f000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1419,7 +1504,7 @@ replicator@8046000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x08046000 0x1000>; + reg = <0x0 0x08046000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1445,7 +1530,7 @@ etf@8047000 { compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x08047000 0x1000>; + reg = <0x0 0x08047000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1471,7 +1556,7 @@ etr@8048000 { compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x08048000 0x1000>; + reg = <0x0 0x08048000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1489,7 +1574,7 @@ funnel@8041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x08041000 0x1000>; + reg = <0x0 0x08041000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1515,7 +1600,7 @@ funnel@8042000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x08042000 0x1000>; + reg = <0x0 0x08042000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1541,7 +1626,7 @@ funnel@8045000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x08045000 0x1000>; + reg = <0x0 0x08045000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1578,7 +1663,7 @@ etm@9040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x09040000 0x1000>; + reg = <0x0 0x09040000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1599,7 +1684,7 @@ etm@9140000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x09140000 0x1000>; + reg = <0x0 0x09140000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1620,7 +1705,7 @@ etm@9240000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x09240000 0x1000>; + reg = <0x0 0x09240000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1641,7 +1726,7 @@ etm@9340000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x09340000 0x1000>; + reg = <0x0 0x09340000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1662,7 +1747,7 @@ etm@9440000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x09440000 0x1000>; + reg = <0x0 0x09440000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1683,7 +1768,7 @@ etm@9540000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x09540000 0x1000>; + reg = <0x0 0x09540000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1704,7 +1789,7 @@ etm@9640000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x09640000 0x1000>; + reg = <0x0 0x09640000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1725,7 +1810,7 @@ etm@9740000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x09740000 0x1000>; + reg = <0x0 0x09740000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1746,7 +1831,7 @@ funnel@9800000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x09800000 0x1000>; + reg = <0x0 0x09800000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1825,7 +1910,7 @@ funnel@9810000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x09810000 0x1000>; + reg = <0x0 0x09810000 0x0 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1851,7 +1936,7 @@ apps_smmu: iommu@c600000 { compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0x0c600000 0x80000>; + reg = <0x0 0x0c600000 0x0 0x80000>; #iommu-cells = <2>; #global-interrupts = <1>; @@ -1924,7 +2009,7 @@ wifi: wifi@c800000 { compatible = "qcom,wcn3990-wifi"; - reg = <0x0c800000 0x800000>; + reg = <0x0 0x0c800000 0x0 0x800000>; reg-names = "membase"; memory-region = <&wlan_msa_mem>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, @@ -1944,65 +2029,72 @@ status = "disabled"; }; + watchdog@f017000 { + compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; + reg = <0x0 0x0f017000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; + }; + apcs_glb: mailbox@f111000 { compatible = "qcom,sm6115-apcs-hmss-global"; - reg = <0x0f111000 0x1000>; + reg = <0x0 0x0f111000 0x0 0x1000>; #mbox-cells = <1>; }; timer@f120000 { compatible = "arm,armv7-timer-mem"; - reg = <0x0f120000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x0 0x0f120000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; ranges; clock-frequency = <19200000>; frame@f121000 { - reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; + reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; }; frame@f123000 { - reg = <0x0f123000 0x1000>; + reg = <0x0 0x0f123000 0x0 0x1000>; frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f124000 { - reg = <0x0f124000 0x1000>; + reg = <0x0 0x0f124000 0x0 0x1000>; frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f125000 { - reg = <0x0f125000 0x1000>; + reg = <0x0 0x0f125000 0x0 0x1000>; frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f126000 { - reg = <0x0f126000 0x1000>; + reg = <0x0 0x0f126000 0x0 0x1000>; frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f127000 { - reg = <0x0f127000 0x1000>; + reg = <0x0 0x0f127000 0x0 0x1000>; frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f128000 { - reg = <0x0f128000 0x1000>; + reg = <0x0 0x0f128000 0x0 0x1000>; frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -2011,7 +2103,8 @@ intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; - reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; + reg = <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f300000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; interrupt-parent = <&intc>; @@ -2022,7 +2115,8 @@ cpufreq_hw: cpufreq@f521000 { compatible = "qcom,cpufreq-hw"; - reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>; + reg = <0x0 0x0f521000 0x0 0x1000>, + <0x0 0x0f523000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 8224adb99948..1e1d366c92c1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,gcc-sm6350.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm6350-camcc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,icc.h> @@ -13,6 +14,7 @@ #include <dt-bindings/interconnect/qcom,sm6350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -1314,49 +1316,26 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sc7180-qmp-usb3-dp-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x40>, - <0 0x088ea000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1_qmpphy: phy@88e8000 { + compatible = "qcom,sm6350-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&xo_board>, - <&rpmhcc RPMH_QLINK_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: usb3-phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + #clock-cells = <1>; + #phy-cells = <1>; - dp_phy: dp-phy@88ea200 { - reg = <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eaa00 0 0x200>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>; - #phy-cells = <0>; - #clock-cells = <1>; - }; + status = "disabled"; }; dc_noc: interconnect@9160000 { @@ -1430,11 +1409,109 @@ snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; }; }; + cci0: cci@ac4a000 { + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4a000 0 0x1000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>, + <&camcc CAMCC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4b000 0 0x1000>; + interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>, + <&camcc CAMCC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-0 = <&cci2_default>; + pinctrl-1 = <&cci2_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm6350-camcc"; + reg = <0 0x0ad00000 0 0x16000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; @@ -1513,6 +1590,48 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + cci0_default: cci0-default-state { + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio41", "gpio42"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio41", "gpio42"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_default: cci2-default-state { + pins = "gpio43", "gpio44"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_sleep: cci2-sleep-state { + pins = "gpio43", "gpio44"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + sdc2_off_state: sdc2-off-state { clk-pins { pins = "sdc2_clk"; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index b86a1c6f08be..f7602e93121a 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -115,7 +115,7 @@ }; &apps_rsc { - pm6350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm6350-rpmh-regulators"; qcom,pmic-id = "a"; @@ -244,7 +244,7 @@ }; }; - pm6150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm6150l-rpmh-regulators"; qcom,pmic-id = "e"; @@ -334,6 +334,26 @@ }; }; +&cci0 { + status = "okay"; +}; + +&cci0_i2c0 { + /* IMX582 @ 0x1a */ +}; + +&cci0_i2c1 { + /* IMX582 @ 0x1a */ +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + /* IMX576 @ 0x10 */ +}; + &cdsp { status = "okay"; firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 3331ee957d64..8f014a232526 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -56,7 +56,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -211,7 +211,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -324,7 +324,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index 5397fba9417b..69024f7c7f10 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -61,7 +61,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -216,7 +216,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -329,7 +329,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 46b5cf9a1192..eff995a07ab7 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -51,7 +51,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -206,7 +206,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -319,7 +319,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index 64602748c657..ff77cc3c879a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -173,7 +173,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -306,7 +306,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 632e98193d27..0aee7f8658b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -65,7 +65,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -199,7 +199,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -310,7 +310,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 0991b34a8e49..e54cdc8bc31f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -187,7 +187,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -321,7 +321,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -432,7 +432,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; @@ -759,6 +759,8 @@ }; &swr0 { + status = "okay"; + left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; @@ -892,3 +894,7 @@ &venus { status = "okay"; }; + +&wsamacro { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index e76d0ef5aec9..b9c982a059df 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -123,7 +123,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -247,7 +247,7 @@ * ab: 4600000-6100000 * ibb: 800000-5400000 */ - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -360,7 +360,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts new file mode 100644 index 000000000000..acaa99c5ff8b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts @@ -0,0 +1,630 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com> + */ + +/dts-v1/; + +#include <dt-bindings/arm/qcom,ids.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8250.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" +#include "pm8009.dtsi" + +/* + * Delete following upstream (sm8250.dtsi) reserved + * memory mappings which are different on this device. + */ +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_secure_heap; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &xbl_aop_mem; + +/ { + model = "Xiaomi Mi Pad 5 Pro"; + compatible = "xiaomi,elish", "qcom,sm8250"; + classis-type = "tablet"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <QCOM_ID_SM8250 0x20001>; /* SM8250 v2.1 */ + qcom,board-id = <0x10008 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 0x2300000>; + width = <1600>; + height = <2560>; + stride = <(1600 * 4)>; + format = "a8r8g8b8"; + }; + }; + + battery_l: battery-l { + compatible = "simple-battery"; + voltage-min-design-microvolt = <3870000>; + energy-full-design-microwatt-hours = <16600000>; + charge-full-design-microamp-hours = <4300000>; + }; + + battery_r: battery-r { + compatible = "simple-battery"; + voltage-min-design-microvolt = <3870000>; + energy-full-design-microwatt-hours = <16600000>; + charge-full-design-microamp-hours = <4300000>; + }; + + bl_vddpos_5p5: bl-vddpos-regulator { + compatible = "regulator-fixed"; + regulator-name = "bl_vddpos_5p5"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + bl_vddneg_5p5: bl-vddneg-regulator { + compatible = "regulator-fixed"; + regulator-name = "bl_vddneg_5p5"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 131 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-vol-up { + label = "Volume Up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* S6c is really ebi.lvl but it's there for supply map completeness sake. */ + vreg_s6c_0p88: smpc6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s6c_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + xbl_aop_mem: xbl-aop@80700000 { + reg = <0x0 0x80600000 0x0 0x260000>; + no-map; + }; + + slpi_mem: slpi@88c00000 { + reg = <0x0 0x88c00000 0x0 0x2f00000>; + no-map; + }; + + adsp_mem: adsp@8bb00000 { + reg = <0x0 0x8bb00000 0x0 0x2500000>; + no-map; + }; + + spss_mem: spss@8e000000 { + reg = <0x0 0x8e000000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: cdsp-secure-heap@8e100000 { + reg = <0x0 0x8e100000 0x0 0x4600000>; + no-map; + }; + + cont_splash_mem: cont-splash@9c000000 { + reg = <0x0 0x9c000000 0x0 0x2300000>; + no-map; + }; + + ramoops@b0000000 { + compatible = "ramoops"; + reg = <0x0 0xb0000000 0x0 0x400000>; + record-size = <0x1000>; + console-size = <0x200000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&adsp { + firmware-name = "qcom/sm8250/xiaomi/elish/adsp.mbn"; + status = "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; + vdd-l6-l9-supply = <&vreg_s8c_1p35>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + /* (S1+S2+S3) - cx.lvl (ARC) */ + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6a_0p95: smps6 { + regulator-name = "vreg_s6a_0p95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L4 - lmx.lvl (ARC) */ + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + /* L7 is unused. */ + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L10 is unused, L11 - lcx.lvl (ARC) */ + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L13 is unused. */ + + vreg_l14a_1p88: ldo14 { + regulator-name = "vreg_l14a_1p88"; + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L15 & L16 are unused. */ + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18a_0p9: ldo18 { + regulator-name = "vreg_l18a_0p9"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* + * Remaining regulators that are not yet supported: + * OLEDB: 4925000-8100000 + * ab: 4600000-6100000 + * ibb: 800000-5400000 + */ + regulators-1 { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p35>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3350000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + + /* + * S1-S6 are ARCs: + * (S1+S2) - gfx.lvl, + * S3 - mx.lvl, + * (S4+S5) - mmcx.lvl, + * S6 - ebi.lvl + */ + + vreg_s7c_0p35: smps7 { + regulator-name = "vreg_s7c_0p35"; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s8c_1p35: smps8 { + regulator-name = "vreg_s8c_1p35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L2-4 are unused. */ + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-name = "vreg_l6c_2p9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c_2p85: ldo7 { + regulator-name = "vreg_l7c_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-name = "vreg_l9c_2p9"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10c_3p3: ldo10 { + regulator-name = "vreg_l10c_3p3"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3296000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_3p0: ldo11 { + regulator-name = "vreg_l11c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + vdd-l2-supply = <&vreg_s8c_1p35>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_s1f_1p2: smps1 { + regulator-name = "vreg_s1f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2f_0p5: smps2 { + regulator-name = "vreg_s2f_0p5"; + regulator-min-microvolt = <512000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L1 is unused. */ + + vreg_l2f_1p3: ldo2 { + regulator-name = "vreg_l2f_1p3"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L3 & L4 are unused. */ + + vreg_l5f_2p8: ldo5 { + regulator-name = "vreg_l5f_2p85"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6f_2p8: ldo6 { + regulator-name = "vreg_l6f_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&cdsp { + firmware-name = "qcom/sm8250/xiaomi/elish/cdsp.mbn"; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sm8250/xiaomi/elish/a650_zap.mbn"; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + fuel-gauge@55 { + compatible = "ti,bq27z561"; + reg = <0x55>; + monitored-battery = <&battery_r>; + }; +}; + +&i2c11 { + clock-frequency = <400000>; + status = "okay"; + + backlight: backlight@11 { + compatible = "kinetic,ktz8866"; + reg = <0x11>; + vddpos-supply = <&bl_vddpos_5p5>; + vddneg-supply = <&bl_vddneg_5p5>; + enable-gpios = <&tlmm 139 GPIO_ACTIVE_HIGH>; + current-num-sinks = <5>; + kinetic,current-ramp-delay-ms = <128>; + kinetic,led-enable-ramp-delay-ms = <1>; + kinetic,enable-lcd-bias; + }; +}; + +&i2c13 { + clock-frequency = <400000>; + status = "okay"; + + fuel-gauge@55 { + compatible = "ti,bq27z561"; + reg = <0x55>; + monitored-battery = <&battery_l>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + status = "okay"; +}; + +&pm8150_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&slpi { + firmware-name = "qcom/sm8250/xiaomi/elish/slpi.mbn"; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <40 4>; +}; + +&usb_1 { + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + maximum-spped = "high-speed"; + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l2a_3p1>; + status = "okay"; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l17a_3p0>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <800000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <800000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sm8250/elish/venus.mbn"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 64c08c399ab8..f69fa68a1222 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2239,6 +2239,8 @@ pinctrl-names = "default"; pinctrl-0 = <&wsa_swr_active>; + + status = "disabled"; }; swr0: soundwire-controller@3250000 { @@ -2259,6 +2261,8 @@ #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; + + status = "disabled"; }; audiocc: clock-controller@3300000 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 5a4c4ea4d122..54654eb75c28 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -73,7 +73,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -178,7 +178,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -309,7 +309,7 @@ reg = <0>; lt9611_a: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -723,15 +723,15 @@ }; lt9611_state: lt9611-state { - rst { + rst-pins { pins = "gpio48"; - function = "normal"; + function = "gpio"; output-high; input-disable; }; - irq { + irq-pins { pins = "gpio50"; function = "gpio"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 00f16cde6c4a..b536ae36ae6d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -44,7 +44,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -135,7 +135,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index f70e0de0509c..d21d2aacf201 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -43,7 +43,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -134,7 +134,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e466dd839065..0a422637b61f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1031,8 +1031,6 @@ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -2549,8 +2547,8 @@ <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC2_BCR>; - interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; power-domains = <&rpmhpd SM8350_CX>; @@ -2876,14 +2874,21 @@ port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; mdss_dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -2913,6 +2918,9 @@ phys = <&mdss_dsi0_phy>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; dsi0_opp_table: opp-table { @@ -2945,24 +2953,24 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; mdss_dsi0_phy: phy@ae94400 { - compatible = "qcom,dsi-phy-5nm-8350"; + compatible = "qcom,sm8350-dsi-phy-5nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, - <0 0x0ae94900 0 0x260>; + <0 0x0ae94900 0 0x27c>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -2978,12 +2986,12 @@ }; mdss_dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4>; + interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, @@ -3008,6 +3016,9 @@ phys = <&mdss_dsi1_phy>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; dsi1_opp_table: opp-table { @@ -3040,23 +3051,24 @@ port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; mdss_dsi1_phy: phy@ae96400 { - compatible = "qcom,dsi-phy-5nm-8350"; + compatible = "qcom,sm8350-dsi-phy-5nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, - <0 0x0ae96900 0 0x260>; + <0 0x0ae96900 0 0x27c>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -3077,7 +3089,7 @@ reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, - <0>, <0>, + <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, <0>, <0>; clock-names = "bi_tcxo", diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 5bdc2c1159ae..feef3837e4cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -99,7 +99,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -190,7 +190,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -303,7 +303,7 @@ }; }; - pm8450-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8450-rpmh-regulators"; qcom,pmic-id = "h"; @@ -346,7 +346,7 @@ }; - pmr735a-rpmh-regulators { + regulators-3 { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 134ffdfc2c63..f7592946c783 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -39,7 +39,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -130,7 +130,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -242,7 +242,7 @@ }; }; - pm8450-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8450-rpmh-regulators"; qcom,pmic-id = "h"; @@ -285,7 +285,7 @@ }; - pmr735a-rpmh-regulators { + regulators-3 { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index 53d0ee2dbfa9..67538b5a557e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -116,7 +116,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -212,7 +212,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -348,7 +348,7 @@ }; }; - pm8450-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8450-rpmh-regulators"; qcom,pmic-id = "h"; @@ -392,7 +392,7 @@ }; }; - pmr735a-rpmh-regulators { + regulators-3 { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; @@ -694,17 +694,17 @@ }; &remoteproc_adsp { - firmware-name = "qcom/sm8350/Sony/nagara/adsp.mbn"; + firmware-name = "qcom/sm8450/Sony/nagara/adsp.mbn"; status = "okay"; }; &remoteproc_cdsp { - firmware-name = "qcom/sm8350/Sony/nagara/cdsp.mbn"; + firmware-name = "qcom/sm8450/Sony/nagara/cdsp.mbn"; status = "okay"; }; &remoteproc_slpi { - firmware-name = "qcom/sm8350/Sony/nagara/slpi.mbn"; + firmware-name = "qcom/sm8450/Sony/nagara/slpi.mbn"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d66dcd8fe61f..1a744a33bcf4 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1017,8 +1017,6 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart20_default>; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -1411,8 +1409,6 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; }; @@ -2873,7 +2869,7 @@ }; mdss_dsi0_phy: phy@ae94400 { - compatible = "qcom,dsi-phy-5nm-8450"; + compatible = "qcom,sm8450-dsi-phy-5nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94900 0 0x260>; @@ -2946,7 +2942,7 @@ }; mdss_dsi1_phy: phy@ae96400 { - compatible = "qcom,dsi-phy-5nm-8450"; + compatible = "qcom,sm8450-dsi-phy-5nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, <0 0x0ae96900 0 0x260>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 725d3bc3ee72..5db6e789e6b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -47,7 +47,7 @@ vdd-bob2-supply = <&vph_pwr>; vdd-l2-l13-l14-supply = <&vreg_bob1>; vdd-l3-supply = <&vreg_s4g_1p3>; - vdd-l6-l16-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; vdd-l6-l7-supply = <&vreg_bob1>; vdd-l8-l9-supply = <&vreg_bob1>; vdd-l11-supply = <&vreg_s4g_1p3>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 6ff135191ee0..9910006c32aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -13,7 +13,9 @@ #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/thermal/thermal.h> @@ -1582,8 +1584,6 @@ interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; }; @@ -1996,6 +1996,19 @@ }; }; + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,sm8550-lpass-lpi-pinctrl"; + reg = <0 0x06e80000 0 0x20000>, + <0 0x0725a000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,sm8550-lpass-lpiaon-noc"; reg = <0 0x07400000 0 0x19080>; @@ -2175,7 +2188,7 @@ }; mdss_dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -2269,7 +2282,7 @@ }; mdss_dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; @@ -2395,8 +2408,8 @@ power-domains = <&gcc USB3_PHY_GDSC>; - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; @@ -2503,7 +2516,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupt-parent = <&ipcc>; @@ -3055,7 +3068,7 @@ }; apps_smmu: iommu@15000000 { - compatible = "qcom,smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; @@ -3513,6 +3526,46 @@ <&apps_smmu 0x1067 0x0>; }; }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1061 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 75f63a58507a..cd689b782f97 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -69,6 +69,15 @@ config INTERCONNECT_QCOM_QCS404 This is a driver for the Qualcomm Network-on-Chip on qcs404-based platforms. +config INTERCONNECT_QCOM_QDU1000 + tristate "Qualcomm QDU1000/QRU1000 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on QDU1000-based + and QRU1000-based platforms. + config INTERCONNECT_QCOM_RPMH_POSSIBLE tristate default INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index c720e6742ea8..3fd4c2713c4a 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -11,6 +11,7 @@ qnoc-msm8996-objs := msm8996.o icc-osm-l3-objs := osm-l3.o qnoc-qcm2290-objs := qcm2290.o qnoc-qcs404-objs := qcs404.o +qnoc-qdu1000-objs := qdu1000.o icc-rpmh-obj := icc-rpmh.o qnoc-sc7180-objs := sc7180.o qnoc-sc7280-objs := sc7280.o @@ -36,6 +37,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o +obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c new file mode 100644 index 000000000000..a4cf559de2b0 --- /dev/null +++ b/drivers/interconnect/qcom/qdu1000.c @@ -0,0 +1,1067 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> + +#include "bcm-voter.h" +#include "icc-common.h" +#include "icc-rpmh.h" +#include "qdu1000.h" + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = QDU1000_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = QDU1000_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = QDU1000_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = QDU1000_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 4, + .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, + QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_ecpri_dma = { + .name = "qnm_ecpri_dma", + .id = QDU1000_MASTER_GEMNOC_ECPRI_DMA, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_fec_2_gemnoc = { + .name = "qnm_fec_2_gemnoc", + .id = QDU1000_MASTER_FEC_2_GEMNOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = QDU1000_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 64, + .num_links = 3, + .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, + QDU1000_SLAVE_GEMNOC_MODEM_CNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = QDU1000_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = QDU1000_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 4, + .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, + QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qxm_mdsp = { + .name = "qxm_mdsp", + .id = QDU1000_MASTER_MSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, + QDU1000_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = QDU1000_MASTER_LLCC, + .channels = 8, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qhm_gic = { + .name = "qhm_gic", + .id = QDU1000_MASTER_GIC_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = QDU1000_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qhm_qpic = { + .name = "qhm_qpic", + .id = QDU1000_MASTER_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = QDU1000_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = QDU1000_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = QDU1000_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_system_noc_cfg = { + .name = "qhm_system_noc_cfg", + .id = QDU1000_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre_noc = { + .name = "qnm_aggre_noc", + .id = QDU1000_MASTER_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre_noc_gsi = { + .name = "qnm_aggre_noc_gsi", + .id = QDU1000_MASTER_ANOC_GSI, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = QDU1000_MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 36, + .links = { QDU1000_SLAVE_AHB2PHY_SOUTH, QDU1000_SLAVE_AHB2PHY_NORTH, + QDU1000_SLAVE_AHB2PHY_EAST, QDU1000_SLAVE_AOSS, + QDU1000_SLAVE_CLK_CTL, QDU1000_SLAVE_RBCPR_CX_CFG, + QDU1000_SLAVE_RBCPR_MX_CFG, QDU1000_SLAVE_CRYPTO_0_CFG, + QDU1000_SLAVE_ECPRI_CFG, QDU1000_SLAVE_IMEM_CFG, + QDU1000_SLAVE_IPC_ROUTER_CFG, QDU1000_SLAVE_CNOC_MSS, + QDU1000_SLAVE_PCIE_CFG, QDU1000_SLAVE_PDM, + QDU1000_SLAVE_PIMEM_CFG, QDU1000_SLAVE_PRNG, + QDU1000_SLAVE_QDSS_CFG, QDU1000_SLAVE_QPIC, + QDU1000_SLAVE_QSPI_0, QDU1000_SLAVE_QUP_0, + QDU1000_SLAVE_QUP_1, QDU1000_SLAVE_SDCC_2, + QDU1000_SLAVE_SMBUS_CFG, QDU1000_SLAVE_SNOC_CFG, + QDU1000_SLAVE_TCSR, QDU1000_SLAVE_TLMM, + QDU1000_SLAVE_TME_CFG, QDU1000_SLAVE_TSC_CFG, + QDU1000_SLAVE_USB3_0, QDU1000_SLAVE_VSENSE_CTRL_CFG, + QDU1000_SLAVE_DDRSS_CFG, QDU1000_SLAVE_IMEM, + QDU1000_SLAVE_PIMEM, QDU1000_SLAVE_ETHERNET_SS, + QDU1000_SLAVE_QDSS_STM, QDU1000_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc_modem_slave = { + .name = "qnm_gemnoc_modem_slave", + .id = QDU1000_MASTER_GEMNOC_MODEM_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { QDU1000_SLAVE_MODEM_OFFLINE }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = QDU1000_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { QDU1000_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = QDU1000_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ecpri_gsi = { + .name = "qxm_ecpri_gsi", + .id = QDU1000_MASTER_ECPRI_GSI, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { QDU1000_SLAVE_ANOC_SNOC_GSI, QDU1000_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = QDU1000_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_ecpri_dma = { + .name = "xm_ecpri_dma", + .id = QDU1000_MASTER_SNOC_ECPRI_DMA, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { QDU1000_SLAVE_ECPRI_GEMNOC, QDU1000_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = QDU1000_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_pcie = { + .name = "xm_pcie", + .id = QDU1000_MASTER_PCIE, + .channels = 1, + .buswidth = 64, + .num_links = 1, + .links = { QDU1000_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr0 = { + .name = "xm_qdss_etr0", + .id = QDU1000_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node xm_qdss_etr1 = { + .name = "xm_qdss_etr1", + .id = QDU1000_MASTER_QDSS_ETR_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node xm_sdc = { + .name = "xm_sdc", + .id = QDU1000_MASTER_SDCC_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .id = QDU1000_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = QDU1000_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = QDU1000_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .id = QDU1000_SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { QDU1000_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = QDU1000_SLAVE_LLCC, + .channels = 8, + .buswidth = 16, + .num_links = 1, + .links = { QDU1000_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_modem_slave = { + .name = "qns_modem_slave", + .id = QDU1000_SLAVE_GEMNOC_MODEM_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { QDU1000_MASTER_GEMNOC_MODEM_CNOC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = QDU1000_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { QDU1000_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = QDU1000_SLAVE_EBI1, + .channels = 8, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy0_south = { + .name = "qhs_ahb2phy0_south", + .id = QDU1000_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy1_north = { + .name = "qhs_ahb2phy1_north", + .id = QDU1000_SLAVE_AHB2PHY_NORTH, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy2_east = { + .name = "qhs_ahb2phy2_east", + .id = QDU1000_SLAVE_AHB2PHY_EAST, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = QDU1000_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = QDU1000_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = QDU1000_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = QDU1000_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_crypto_cfg = { + .name = "qhs_crypto_cfg", + .id = QDU1000_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ecpri_cfg = { + .name = "qhs_ecpri_cfg", + .id = QDU1000_SLAVE_ECPRI_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = QDU1000_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = QDU1000_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = QDU1000_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie_cfg = { + .name = "qhs_pcie_cfg", + .id = QDU1000_SLAVE_PCIE_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = QDU1000_SLAVE_PDM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = QDU1000_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = QDU1000_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = QDU1000_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qpic = { + .name = "qhs_qpic", + .id = QDU1000_SLAVE_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = QDU1000_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = QDU1000_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = QDU1000_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = QDU1000_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_smbus_cfg = { + .name = "qhs_smbus_cfg", + .id = QDU1000_SLAVE_SMBUS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_system_noc_cfg = { + .name = "qhs_system_noc_cfg", + .id = QDU1000_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { QDU1000_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = QDU1000_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = QDU1000_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tme_cfg = { + .name = "qhs_tme_cfg", + .id = QDU1000_SLAVE_TME_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tsc_cfg = { + .name = "qhs_tsc_cfg", + .id = QDU1000_SLAVE_TSC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = QDU1000_SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = QDU1000_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = QDU1000_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_anoc_snoc_gsi = { + .name = "qns_anoc_snoc_gsi", + .id = QDU1000_SLAVE_ANOC_SNOC_GSI, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_MASTER_ANOC_GSI }, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = QDU1000_SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_ecpri_gemnoc = { + .name = "qns_ecpri_gemnoc", + .id = QDU1000_SLAVE_ECPRI_GEMNOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { QDU1000_MASTER_GEMNOC_ECPRI_DMA }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = QDU1000_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { QDU1000_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = QDU1000_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { QDU1000_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_modem = { + .name = "qns_modem", + .id = QDU1000_SLAVE_MODEM_OFFLINE, + .channels = 1, + .buswidth = 32, + .num_links = 0, +}; + +static struct qcom_icc_node qns_pcie_gemnoc = { + .name = "qns_pcie_gemnoc", + .id = QDU1000_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 64, + .num_links = 1, + .links = { QDU1000_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = QDU1000_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = QDU1000_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_system_noc = { + .name = "srvc_system_noc", + .id = QDU1000_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_ethernet_ss = { + .name = "xs_ethernet_ss", + .id = QDU1000_SLAVE_ETHERNET_SS, + .channels = 1, + .buswidth = 32, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .id = QDU1000_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 64, + .num_links = 0, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = QDU1000_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = QDU1000_SLAVE_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .num_nodes = 44, + .nodes = { &qhm_qpic, &qhm_qspi, + &qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave, + &qnm_gemnoc_pcie, &xm_sdc, + &xm_usb3, &qhs_ahb2phy0_south, + &qhs_ahb2phy1_north, &qhs_ahb2phy2_east, + &qhs_aoss, &qhs_clk_ctl, + &qhs_cpr_cx, &qhs_cpr_mx, + &qhs_crypto_cfg, &qhs_ecpri_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_pcie_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_sdc2, &qhs_smbus_cfg, + &qhs_system_noc_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_tsc_cfg, &qhs_usb3, + &qhs_vsense_ctrl_cfg, &qns_ddrss_cfg, + &qns_modem, &qxs_imem, + &qxs_pimem, &xs_ethernet_ss, + &xs_qdss_stm, &xs_sys_tcu_cfg + }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .num_nodes = 2, + .nodes = { &qup0_core_slave, &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .num_nodes = 11, + .nodes = { &alm_sys_tcu, &chm_apps, + &qnm_ecpri_dma, &qnm_fec_2_gemnoc, + &qnm_pcie, &qnm_snoc_gc, + &qnm_snoc_sf, &qxm_mdsp, + &qns_gem_noc_cnoc, &qns_modem_slave, + &qns_pcie + }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .num_nodes = 6, + .nodes = { &qhm_gic, &qxm_pimem, + &xm_gic, &xm_qdss_etr0, + &xm_qdss_etr1, &qns_gemnoc_gc + }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 5, + .nodes = { &qnm_aggre_noc, &qxm_ecpri_gsi, + &xm_ecpri_dma, &qns_anoc_snoc_gsi, + &qns_ecpri_gemnoc + }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .num_nodes = 2, + .nodes = { &qns_pcie_gemnoc, &xs_pcie }, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qup0, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, +}; + +static const struct qcom_icc_desc qdu1000_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GEMNOC_ECPRI_DMA] = &qnm_ecpri_dma, + [MASTER_FEC_2_GEMNOC] = &qnm_fec_2_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_MSS_PROC] = &qxm_mdsp, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_GEMNOC_MODEM_CNOC] = &qns_modem_slave, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, +}; + +static const struct qcom_icc_desc qdu1000_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc qdu1000_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_ce0, + &bcm_cn0, + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn7, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_GIC_AHB] = &qhm_gic, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QPIC] = &qhm_qpic, + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_SNOC_CFG] = &qhm_system_noc_cfg, + [MASTER_ANOC_SNOC] = &qnm_aggre_noc, + [MASTER_ANOC_GSI] = &qnm_aggre_noc_gsi, + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEMNOC_MODEM_CNOC] = &qnm_gemnoc_modem_slave, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_ECPRI_GSI] = &qxm_ecpri_gsi, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_SNOC_ECPRI_DMA] = &xm_ecpri_dma, + [MASTER_GIC] = &xm_gic, + [MASTER_PCIE] = &xm_pcie, + [MASTER_QDSS_ETR] = &xm_qdss_etr0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr1, + [MASTER_SDCC_1] = &xm_sdc, + [MASTER_USB3] = &xm_usb3, + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0_south, + [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1_north, + [SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy2_east, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg, + [SLAVE_ECPRI_CFG] = &qhs_ecpri_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QPIC] = &qhs_qpic, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SMBUS_CFG] = &qhs_smbus_cfg, + [SLAVE_SNOC_CFG] = &qhs_system_noc_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_TME_CFG] = &qhs_tme_cfg, + [SLAVE_TSC_CFG] = &qhs_tsc_cfg, + [SLAVE_USB3_0] = &qhs_usb3, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, + [SLAVE_ANOC_SNOC_GSI] = &qns_anoc_snoc_gsi, + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, + [SLAVE_ECPRI_GEMNOC] = &qns_ecpri_gemnoc, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_MODEM_OFFLINE] = &qns_modem, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_SNOC] = &srvc_system_noc, + [SLAVE_ETHERNET_SS] = &xs_ethernet_ss, + [SLAVE_PCIE_0] = &xs_pcie, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc qdu1000_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static int qnoc_probe(struct platform_device *pdev) +{ + int ret; + + ret = qcom_icc_rpmh_probe(pdev); + if (ret) + dev_err(&pdev->dev, "failed to register ICC provider\n"); + + return ret; +} + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,qdu1000-clk-virt", + .data = &qdu1000_clk_virt + }, + { .compatible = "qcom,qdu1000-gem-noc", + .data = &qdu1000_gem_noc + }, + { .compatible = "qcom,qdu1000-mc-virt", + .data = &qdu1000_mc_virt + }, + { .compatible = "qcom,qdu1000-system-noc", + .data = &qdu1000_system_noc + }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qnoc_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-qdu1000", + .of_match_table = qnoc_of_match, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("QDU1000 NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/qdu1000.h b/drivers/interconnect/qcom/qdu1000.h new file mode 100644 index 000000000000..e75a6419df23 --- /dev/null +++ b/drivers/interconnect/qcom/qdu1000.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_QDU1000_H +#define __DRIVERS_INTERCONNECT_QCOM_QDU1000_H + +#define QDU1000_MASTER_SYS_TCU 0 +#define QDU1000_MASTER_APPSS_PROC 1 +#define QDU1000_MASTER_LLCC 2 +#define QDU1000_MASTER_GIC_AHB 3 +#define QDU1000_MASTER_QDSS_BAM 4 +#define QDU1000_MASTER_QPIC 5 +#define QDU1000_MASTER_QSPI_0 6 +#define QDU1000_MASTER_QUP_0 7 +#define QDU1000_MASTER_QUP_1 8 +#define QDU1000_MASTER_SNOC_CFG 9 +#define QDU1000_MASTER_ANOC_SNOC 10 +#define QDU1000_MASTER_ANOC_GSI 11 +#define QDU1000_MASTER_GEMNOC_ECPRI_DMA 12 +#define QDU1000_MASTER_FEC_2_GEMNOC 13 +#define QDU1000_MASTER_GEM_NOC_CNOC 14 +#define QDU1000_MASTER_GEMNOC_MODEM_CNOC 15 +#define QDU1000_MASTER_GEM_NOC_PCIE_SNOC 16 +#define QDU1000_MASTER_ANOC_PCIE_GEM_NOC 17 +#define QDU1000_MASTER_SNOC_GC_MEM_NOC 18 +#define QDU1000_MASTER_SNOC_SF_MEM_NOC 19 +#define QDU1000_MASTER_QUP_CORE_0 20 +#define QDU1000_MASTER_QUP_CORE_1 21 +#define QDU1000_MASTER_CRYPTO 22 +#define QDU1000_MASTER_ECPRI_GSI 23 +#define QDU1000_MASTER_MSS_PROC 24 +#define QDU1000_MASTER_PIMEM 25 +#define QDU1000_MASTER_SNOC_ECPRI_DMA 26 +#define QDU1000_MASTER_GIC 27 +#define QDU1000_MASTER_PCIE 28 +#define QDU1000_MASTER_QDSS_ETR 29 +#define QDU1000_MASTER_QDSS_ETR_1 30 +#define QDU1000_MASTER_SDCC_1 31 +#define QDU1000_MASTER_USB3 32 +#define QDU1000_SLAVE_EBI1 512 +#define QDU1000_SLAVE_AHB2PHY_SOUTH 513 +#define QDU1000_SLAVE_AHB2PHY_NORTH 514 +#define QDU1000_SLAVE_AHB2PHY_EAST 515 +#define QDU1000_SLAVE_AOSS 516 +#define QDU1000_SLAVE_CLK_CTL 517 +#define QDU1000_SLAVE_RBCPR_CX_CFG 518 +#define QDU1000_SLAVE_RBCPR_MX_CFG 519 +#define QDU1000_SLAVE_CRYPTO_0_CFG 520 +#define QDU1000_SLAVE_ECPRI_CFG 521 +#define QDU1000_SLAVE_IMEM_CFG 522 +#define QDU1000_SLAVE_IPC_ROUTER_CFG 523 +#define QDU1000_SLAVE_CNOC_MSS 524 +#define QDU1000_SLAVE_PCIE_CFG 525 +#define QDU1000_SLAVE_PDM 526 +#define QDU1000_SLAVE_PIMEM_CFG 527 +#define QDU1000_SLAVE_PRNG 528 +#define QDU1000_SLAVE_QDSS_CFG 529 +#define QDU1000_SLAVE_QPIC 530 +#define QDU1000_SLAVE_QSPI_0 531 +#define QDU1000_SLAVE_QUP_0 532 +#define QDU1000_SLAVE_QUP_1 533 +#define QDU1000_SLAVE_SDCC_2 534 +#define QDU1000_SLAVE_SMBUS_CFG 535 +#define QDU1000_SLAVE_SNOC_CFG 536 +#define QDU1000_SLAVE_TCSR 537 +#define QDU1000_SLAVE_TLMM 538 +#define QDU1000_SLAVE_TME_CFG 539 +#define QDU1000_SLAVE_TSC_CFG 540 +#define QDU1000_SLAVE_USB3_0 541 +#define QDU1000_SLAVE_VSENSE_CTRL_CFG 542 +#define QDU1000_SLAVE_A1NOC_SNOC 543 +#define QDU1000_SLAVE_ANOC_SNOC_GSI 544 +#define QDU1000_SLAVE_DDRSS_CFG 545 +#define QDU1000_SLAVE_ECPRI_GEMNOC 546 +#define QDU1000_SLAVE_GEM_NOC_CNOC 547 +#define QDU1000_SLAVE_SNOC_GEM_NOC_GC 548 +#define QDU1000_SLAVE_SNOC_GEM_NOC_SF 549 +#define QDU1000_SLAVE_LLCC 550 +#define QDU1000_SLAVE_MODEM_OFFLINE 551 +#define QDU1000_SLAVE_GEMNOC_MODEM_CNOC 552 +#define QDU1000_SLAVE_MEM_NOC_PCIE_SNOC 553 +#define QDU1000_SLAVE_ANOC_PCIE_GEM_NOC 554 +#define QDU1000_SLAVE_QUP_CORE_0 555 +#define QDU1000_SLAVE_QUP_CORE_1 556 +#define QDU1000_SLAVE_IMEM 557 +#define QDU1000_SLAVE_PIMEM 558 +#define QDU1000_SLAVE_SERVICE_SNOC 559 +#define QDU1000_SLAVE_ETHERNET_SS 560 +#define QDU1000_SLAVE_PCIE_0 561 +#define QDU1000_SLAVE_QDSS_STM 562 +#define QDU1000_SLAVE_TCU 563 + +#endif diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h new file mode 100644 index 000000000000..ddbc6b825e80 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H +#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL2 3 +#define GCC_GPLL2_OUT_EVEN 4 +#define GCC_GPLL3 5 +#define GCC_GPLL4 6 +#define GCC_GPLL5 7 +#define GCC_GPLL5_OUT_EVEN 8 +#define GCC_GPLL6 9 +#define GCC_GPLL7 10 +#define GCC_GPLL8 11 +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12 +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13 +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14 +#define GCC_BOOT_ROM_AHB_CLK 15 +#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_DDRSS_ECPRI_DMA_CLK 18 +#define GCC_ECPRI_AHB_CLK 19 +#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20 +#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21 +#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22 +#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23 +#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24 +#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25 +#define GCC_ECPRI_XO_CLK 26 +#define GCC_ETH_DBG_SNOC_AXI_CLK 27 +#define GCC_GEMNOC_PCIE_QX_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_PCIE_0_AUX_CLK 35 +#define GCC_PCIE_0_AUX_CLK_SRC 36 +#define GCC_PCIE_0_CFG_AHB_CLK 37 +#define GCC_PCIE_0_CLKREF_EN 38 +#define GCC_PCIE_0_MSTR_AXI_CLK 39 +#define GCC_PCIE_0_PHY_AUX_CLK 40 +#define GCC_PCIE_0_PHY_RCHNG_CLK 41 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_0_PIPE_CLK 43 +#define GCC_PCIE_0_SLV_AXI_CLK 44 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 +#define GCC_PDM2_CLK 46 +#define GCC_PDM2_CLK_SRC 47 +#define GCC_PDM_AHB_CLK 48 +#define GCC_PDM_XO4_CLK 49 +#define GCC_QMIP_ANOC_PCIE_CLK 50 +#define GCC_QMIP_ECPRI_DMA0_CLK 51 +#define GCC_QMIP_ECPRI_DMA1_CLK 52 +#define GCC_QMIP_ECPRI_GSI_CLK 53 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54 +#define GCC_QUPV3_WRAP0_CORE_CLK 55 +#define GCC_QUPV3_WRAP0_S0_CLK 56 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57 +#define GCC_QUPV3_WRAP0_S1_CLK 58 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59 +#define GCC_QUPV3_WRAP0_S2_CLK 60 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61 +#define GCC_QUPV3_WRAP0_S3_CLK 62 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63 +#define GCC_QUPV3_WRAP0_S4_CLK 64 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65 +#define GCC_QUPV3_WRAP0_S5_CLK 66 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S6_CLK 68 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69 +#define GCC_QUPV3_WRAP0_S7_CLK 70 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72 +#define GCC_QUPV3_WRAP1_CORE_CLK 73 +#define GCC_QUPV3_WRAP1_S0_CLK 74 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S1_CLK 76 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S2_CLK 78 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S3_CLK 80 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S4_CLK 82 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83 +#define GCC_QUPV3_WRAP1_S5_CLK 84 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_S6_CLK 86 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87 +#define GCC_QUPV3_WRAP1_S7_CLK 88 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93 +#define GCC_SDCC5_AHB_CLK 94 +#define GCC_SDCC5_APPS_CLK 95 +#define GCC_SDCC5_APPS_CLK_SRC 96 +#define GCC_SDCC5_ICE_CORE_CLK 97 +#define GCC_SDCC5_ICE_CORE_CLK_SRC 98 +#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99 +#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100 +#define GCC_SNOC_CNOC_PCIE_QX_CLK 101 +#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102 +#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103 +#define GCC_TSC_CFG_AHB_CLK 104 +#define GCC_TSC_CLK_SRC 105 +#define GCC_TSC_CNTR_CLK 106 +#define GCC_TSC_ETU_CLK 107 +#define GCC_USB2_CLKREF_EN 108 +#define GCC_USB30_PRIM_MASTER_CLK 109 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113 +#define GCC_USB30_PRIM_SLEEP_CLK 114 +#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +#define GCC_SM_BUS_AHB_CLK 119 +#define GCC_SM_BUS_XO_CLK 120 +#define GCC_SM_BUS_XO_CLK_SRC 121 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122 +#define GCC_ETH_100G_C2C_HM_APB_CLK 123 +#define GCC_ETH_100G_FH_HM_APB_0_CLK 124 +#define GCC_ETH_100G_FH_HM_APB_1_CLK 125 +#define GCC_ETH_100G_FH_HM_APB_2_CLK 126 +#define GCC_ETH_DBG_C2C_HM_APB_CLK 127 +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 +#define GCC_PCIE_0_PIPE_CLK_SRC 129 +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 + +/* GCC resets */ +#define GCC_ECPRI_CC_BCR 0 +#define GCC_ECPRI_SS_BCR 1 +#define GCC_ETH_WRAPPER_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_PHY_CFG_AHB_BCR 8 +#define GCC_PCIE_PHY_COM_BCR 9 +#define GCC_PDM_BCR 10 +#define GCC_QUPV3_WRAPPER_0_BCR 11 +#define GCC_QUPV3_WRAPPER_1_BCR 12 +#define GCC_QUSB2PHY_PRIM_BCR 13 +#define GCC_QUSB2PHY_SEC_BCR 14 +#define GCC_SDCC5_BCR 15 +#define GCC_TCSR_PCIE_BCR 16 +#define GCC_TSC_BCR 17 +#define GCC_USB30_PRIM_BCR 18 +#define GCC_USB3_DP_PHY_PRIM_BCR 19 +#define GCC_USB3_DP_PHY_SEC_BCR 20 +#define GCC_USB3_PHY_PRIM_BCR 21 +#define GCC_USB3_PHY_SEC_BCR 22 +#define GCC_USB3PHY_PHY_PRIM_BCR 23 +#define GCC_USB3PHY_PHY_SEC_BCR 24 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_0_PHY_GDSC 1 +#define USB30_PRIM_GDSC 2 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm6350-camcc.h b/include/dt-bindings/clock/qcom,sm6350-camcc.h new file mode 100644 index 000000000000..c6bcdc8fd485 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6350-camcc.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM6350_H +#define _DT_BINDINGS_CLK_QCOM_CAMCC_SM6350_H + +/* CAMCC clocks */ +#define CAMCC_PLL2_OUT_EARLY 0 +#define CAMCC_PLL0 1 +#define CAMCC_PLL0_OUT_EVEN 2 +#define CAMCC_PLL1 3 +#define CAMCC_PLL1_OUT_EVEN 4 +#define CAMCC_PLL2 5 +#define CAMCC_PLL2_OUT_MAIN 6 +#define CAMCC_PLL3 7 +#define CAMCC_BPS_AHB_CLK 8 +#define CAMCC_BPS_AREG_CLK 9 +#define CAMCC_BPS_AXI_CLK 10 +#define CAMCC_BPS_CLK 11 +#define CAMCC_BPS_CLK_SRC 12 +#define CAMCC_CAMNOC_ATB_CLK 13 +#define CAMCC_CAMNOC_AXI_CLK 14 +#define CAMCC_CCI_0_CLK 15 +#define CAMCC_CCI_0_CLK_SRC 16 +#define CAMCC_CCI_1_CLK 17 +#define CAMCC_CCI_1_CLK_SRC 18 +#define CAMCC_CORE_AHB_CLK 19 +#define CAMCC_CPAS_AHB_CLK 20 +#define CAMCC_CPHY_RX_CLK_SRC 21 +#define CAMCC_CSI0PHYTIMER_CLK 22 +#define CAMCC_CSI0PHYTIMER_CLK_SRC 23 +#define CAMCC_CSI1PHYTIMER_CLK 24 +#define CAMCC_CSI1PHYTIMER_CLK_SRC 25 +#define CAMCC_CSI2PHYTIMER_CLK 26 +#define CAMCC_CSI2PHYTIMER_CLK_SRC 27 +#define CAMCC_CSI3PHYTIMER_CLK 28 +#define CAMCC_CSI3PHYTIMER_CLK_SRC 29 +#define CAMCC_CSIPHY0_CLK 30 +#define CAMCC_CSIPHY1_CLK 31 +#define CAMCC_CSIPHY2_CLK 32 +#define CAMCC_CSIPHY3_CLK 33 +#define CAMCC_FAST_AHB_CLK_SRC 34 +#define CAMCC_ICP_APB_CLK 35 +#define CAMCC_ICP_ATB_CLK 36 +#define CAMCC_ICP_CLK 37 +#define CAMCC_ICP_CLK_SRC 38 +#define CAMCC_ICP_CTI_CLK 39 +#define CAMCC_ICP_TS_CLK 40 +#define CAMCC_IFE_0_AXI_CLK 41 +#define CAMCC_IFE_0_CLK 42 +#define CAMCC_IFE_0_CLK_SRC 43 +#define CAMCC_IFE_0_CPHY_RX_CLK 44 +#define CAMCC_IFE_0_CSID_CLK 45 +#define CAMCC_IFE_0_CSID_CLK_SRC 46 +#define CAMCC_IFE_0_DSP_CLK 47 +#define CAMCC_IFE_1_AXI_CLK 48 +#define CAMCC_IFE_1_CLK 49 +#define CAMCC_IFE_1_CLK_SRC 50 +#define CAMCC_IFE_1_CPHY_RX_CLK 51 +#define CAMCC_IFE_1_CSID_CLK 52 +#define CAMCC_IFE_1_CSID_CLK_SRC 53 +#define CAMCC_IFE_1_DSP_CLK 54 +#define CAMCC_IFE_2_AXI_CLK 55 +#define CAMCC_IFE_2_CLK 56 +#define CAMCC_IFE_2_CLK_SRC 57 +#define CAMCC_IFE_2_CPHY_RX_CLK 58 +#define CAMCC_IFE_2_CSID_CLK 59 +#define CAMCC_IFE_2_CSID_CLK_SRC 60 +#define CAMCC_IFE_2_DSP_CLK 61 +#define CAMCC_IFE_LITE_CLK 62 +#define CAMCC_IFE_LITE_CLK_SRC 63 +#define CAMCC_IFE_LITE_CPHY_RX_CLK 64 +#define CAMCC_IFE_LITE_CSID_CLK 65 +#define CAMCC_IFE_LITE_CSID_CLK_SRC 66 +#define CAMCC_IPE_0_AHB_CLK 67 +#define CAMCC_IPE_0_AREG_CLK 68 +#define CAMCC_IPE_0_AXI_CLK 69 +#define CAMCC_IPE_0_CLK 70 +#define CAMCC_IPE_0_CLK_SRC 71 +#define CAMCC_JPEG_CLK 72 +#define CAMCC_JPEG_CLK_SRC 73 +#define CAMCC_LRME_CLK 74 +#define CAMCC_LRME_CLK_SRC 75 +#define CAMCC_MCLK0_CLK 76 +#define CAMCC_MCLK0_CLK_SRC 77 +#define CAMCC_MCLK1_CLK 78 +#define CAMCC_MCLK1_CLK_SRC 79 +#define CAMCC_MCLK2_CLK 80 +#define CAMCC_MCLK2_CLK_SRC 81 +#define CAMCC_MCLK3_CLK 82 +#define CAMCC_MCLK3_CLK_SRC 83 +#define CAMCC_MCLK4_CLK 84 +#define CAMCC_MCLK4_CLK_SRC 85 +#define CAMCC_SLOW_AHB_CLK_SRC 86 +#define CAMCC_SOC_AHB_CLK 87 +#define CAMCC_SYS_TMR_CLK 88 + +/* GDSCs */ +#define BPS_GDSC 0 +#define IPE_0_GDSC 1 +#define IFE_0_GDSC 2 +#define IFE_1_GDSC 3 +#define IFE_2_GDSC 4 +#define TITAN_TOP_GDSC 5 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h b/include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h new file mode 100644 index 000000000000..7f0ad1571128 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define SLAVE_QUP_CORE_0 2 +#define SLAVE_QUP_CORE_1 3 + +#define MASTER_SYS_TCU 0 +#define MASTER_APPSS_PROC 1 +#define MASTER_GEMNOC_ECPRI_DMA 2 +#define MASTER_FEC_2_GEMNOC 3 +#define MASTER_ANOC_PCIE_GEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_MSS_PROC 7 +#define SLAVE_GEM_NOC_CNOC 8 +#define SLAVE_LLCC 9 +#define SLAVE_GEMNOC_MODEM_CNOC 10 +#define SLAVE_MEM_NOC_PCIE_SNOC 11 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_GIC_AHB 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QPIC 2 +#define MASTER_QSPI_0 3 +#define MASTER_QUP_0 4 +#define MASTER_QUP_1 5 +#define MASTER_SNOC_CFG 6 +#define MASTER_ANOC_SNOC 7 +#define MASTER_ANOC_GSI 8 +#define MASTER_GEM_NOC_CNOC 9 +#define MASTER_GEMNOC_MODEM_CNOC 10 +#define MASTER_GEM_NOC_PCIE_SNOC 11 +#define MASTER_CRYPTO 12 +#define MASTER_ECPRI_GSI 13 +#define MASTER_PIMEM 14 +#define MASTER_SNOC_ECPRI_DMA 15 +#define MASTER_GIC 16 +#define MASTER_PCIE 17 +#define MASTER_QDSS_ETR 18 +#define MASTER_QDSS_ETR_1 19 +#define MASTER_SDCC_1 20 +#define MASTER_USB3 21 +#define SLAVE_AHB2PHY_SOUTH 22 +#define SLAVE_AHB2PHY_NORTH 23 +#define SLAVE_AHB2PHY_EAST 24 +#define SLAVE_AOSS 25 +#define SLAVE_CLK_CTL 26 +#define SLAVE_RBCPR_CX_CFG 27 +#define SLAVE_RBCPR_MX_CFG 28 +#define SLAVE_CRYPTO_0_CFG 29 +#define SLAVE_ECPRI_CFG 30 +#define SLAVE_IMEM_CFG 31 +#define SLAVE_IPC_ROUTER_CFG 32 +#define SLAVE_CNOC_MSS 33 +#define SLAVE_PCIE_CFG 34 +#define SLAVE_PDM 35 +#define SLAVE_PIMEM_CFG 36 +#define SLAVE_PRNG 37 +#define SLAVE_QDSS_CFG 38 +#define SLAVE_QPIC 40 +#define SLAVE_QSPI_0 41 +#define SLAVE_QUP_0 42 +#define SLAVE_QUP_1 43 +#define SLAVE_SDCC_2 44 +#define SLAVE_SMBUS_CFG 45 +#define SLAVE_SNOC_CFG 46 +#define SLAVE_TCSR 47 +#define SLAVE_TLMM 48 +#define SLAVE_TME_CFG 49 +#define SLAVE_TSC_CFG 50 +#define SLAVE_USB3_0 51 +#define SLAVE_VSENSE_CTRL_CFG 52 +#define SLAVE_A1NOC_SNOC 53 +#define SLAVE_ANOC_SNOC_GSI 54 +#define SLAVE_DDRSS_CFG 55 +#define SLAVE_ECPRI_GEMNOC 56 +#define SLAVE_SNOC_GEM_NOC_GC 57 +#define SLAVE_SNOC_GEM_NOC_SF 58 +#define SLAVE_MODEM_OFFLINE 59 +#define SLAVE_ANOC_PCIE_GEM_NOC 60 +#define SLAVE_IMEM 61 +#define SLAVE_PIMEM 62 +#define SLAVE_SERVICE_SNOC 63 +#define SLAVE_ETHERNET_SS 64 +#define SLAVE_PCIE_0 65 +#define SLAVE_QDSS_STM 66 +#define SLAVE_TCU 67 + +#endif |