diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2025-09-23 22:15:55 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-09-23 22:15:57 +0200 |
| commit | 83ae575d6f0e9636c16c62b6ef8980f969574005 (patch) | |
| tree | 682134e23c575e8b405bfd51d755c9feeabfdb62 | |
| parent | 065106185550677bb66231ab0cd0e69fb1d36408 (diff) | |
| parent | ffe6a5d1dd4d4d8af0779526cf4e40522647b25f (diff) | |
Merge tag 'v6.17-next-dts64.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
mt8188:
- change efuse compatible fallback to make GPU DVFS work
- enable SCP core for video decoding and encoding
mt8186:
- add correct touchscreen compatible for tentacruel and krabby
Fixes of DT warnings for many different SoCs and boards.
* tag 'v6.17-next-dts64.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (24 commits)
arm64: dts: mediatek: mt8516-pumpkin: Fix machine compatible
arm64: dts: mediatek: mt8395-kontron-i1200: Fix MT6360 regulator nodes
arm64: dts: mediatek: mt8195-cherry: Add missing regulators to rt5682
arm64: dts: mediatek: mt8195-cherry: Move VBAT-supply to Tomato R1/R2
arm64: dts: mediatek: mt8195: Fix ranges for jpeg enc/decoder nodes
arm64: dts: mediatek: mt8183-kukui: Move DSI panel node to machine dtsis
arm64: dts: mediatek: mt8183: Migrate to display controller OF graph
arm64: dts: mediatek: mt8183-pumpkin: Add power supply for CCI
arm64: dts: mediatek: pumpkin-common: Fix pinctrl node names
arm64: dts: mediatek: mt8183: Fix pinctrl node names
arm64: dts: mediatek: acelink-ew-7886cax: Remove unnecessary cells in spi-nand
arm64: dts: mediatek: mt7986a-bpi-r3: Set interrupt-parent to mdio switch
arm64: dts: mediatek: mt7986a-bpi-r3: Fix SFP I2C node names
arm64: dts: mediatek: mt7986a: Fix PCI-Express T-PHY node address
arm64: dts: mediatek: Fix node name for SYSIRQ controller on all SoCs
arm64: dts: mediatek: mt6795-sony-xperia-m5: Add pinctrl for mmc1/mmc2
arm64: dts: mediatek: mt6795-xperia-m5: Fix mmc0 latch-ck value
arm64: dts: mediatek: mt6795: Add mediatek,infracfg to iommu node
arm64: dts: mediatek: mt6797: Remove bogus id property in i2c nodes
arm64: dts: mediatek: mt6797: Fix pinctrl node names
...
Link: https://lore.kernel.org/r/c0e2e902-2a10-44a7-9592-491ba7382df0@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
29 files changed, 549 insertions, 203 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi index d89858c73ab1..243afbffa21f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6331.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi @@ -6,12 +6,12 @@ #include <dt-bindings/input/input.h> &pwrap { - pmic: mt6331 { + pmic: pmic { compatible = "mediatek,mt6331"; interrupt-controller; #interrupt-cells = <2>; - mt6331regulator: mt6331regulator { + mt6331regulator: regulators { compatible = "mediatek,mt6331-regulator"; mt6331_vdvfs11_reg: buck-vdvfs11 { @@ -258,7 +258,7 @@ }; mt6331_vdig18_reg: ldo-vdig18 { - regulator-name = "dvdd18_dig"; + regulator-name = "vdig18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-ramp-delay = <0>; @@ -266,11 +266,11 @@ }; }; - mt6331rtc: mt6331rtc { + mt6331rtc: rtc { compatible = "mediatek,mt6331-rtc"; }; - mt6331keys: mt6331keys { + mt6331keys: keys { compatible = "mediatek,mt6331-keys"; power { linux,keycodes = <KEY_POWER>; diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi index b55d3fac9bd4..8da5c0a56a02 100644 --- a/arch/arm64/boot/dts/mediatek/mt6755.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6755.dtsi @@ -98,7 +98,7 @@ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 5c579e88e749..70f3375916e8 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -138,7 +138,7 @@ }; - sysirq: intpol-controller@c53a650 { + sysirq: interrupt-controller@c53a650 { compatible = "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 91de920c2245..fccb948cfa45 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -212,7 +212,7 @@ &mmc0 { /* eMMC controller */ - mediatek,latch-ck = <0x14>; /* hs400 */ + mediatek,latch-ck = <4>; /* hs400 */ mediatek,hs200-cmd-int-delay = <1>; mediatek,hs400-cmd-int-delay = <1>; mediatek,hs400-ds-dly3 = <0x1a>; @@ -227,6 +227,8 @@ &mmc1 { /* MicroSD card slot */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -234,6 +236,8 @@ &mmc2 { /* SDIO WiFi on MMC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -311,6 +315,40 @@ }; }; + mmc1_pins_default: microsd-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO171__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO172__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO173__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO174__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO170__FUNC_MSDC1_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + mmc2_pins_default: sdio-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO100__FUNC_MSDC2_DAT0>, + <PINMUX_GPIO101__FUNC_MSDC2_DAT1>, + <PINMUX_GPIO102__FUNC_MSDC2_DAT2>, + <PINMUX_GPIO103__FUNC_MSDC2_DAT3>, + <PINMUX_GPIO105__FUNC_MSDC2_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + nfc_pins: nfc-pins { pins-irq { pinmux = <PINMUX_GPIO3__FUNC_GPIO3>; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index e5e269a660b1..58833e5135c8 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -404,7 +404,7 @@ clock-names = "spi", "wrap"; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; @@ -427,6 +427,7 @@ clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; + mediatek,infracfg = <&infracfg>; mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; power-domains = <&spm MT6795_POWER_DOMAIN_MM>; #iommu-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 0e9d11b4585b..8ac98a378fd6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -135,71 +135,71 @@ gpio-controller; #gpio-cells = <2>; - uart0_pins_a: uart0 { - pins0 { + uart0_pins_a: uart0-pins { + pins-bus { pinmux = <MT6797_GPIO234__FUNC_UTXD0>, <MT6797_GPIO235__FUNC_URXD0>; }; }; - uart1_pins_a: uart1 { - pins1 { + uart1_pins_a: uart1-pins { + pins-bus { pinmux = <MT6797_GPIO232__FUNC_URXD1>, <MT6797_GPIO233__FUNC_UTXD1>; }; }; - i2c0_pins_a: i2c0 { - pins0 { + i2c0_pins_a: i2c0-pins { + pins-bus { pinmux = <MT6797_GPIO37__FUNC_SCL0_0>, <MT6797_GPIO38__FUNC_SDA0_0>; }; }; - i2c1_pins_a: i2c1 { - pins1 { + i2c1_pins_a: i2c1-pins { + pins-bus { pinmux = <MT6797_GPIO55__FUNC_SCL1_0>, <MT6797_GPIO56__FUNC_SDA1_0>; }; }; - i2c2_pins_a: i2c2 { - pins2 { + i2c2_pins_a: i2c2-pins { + pins-bus { pinmux = <MT6797_GPIO96__FUNC_SCL2_0>, <MT6797_GPIO95__FUNC_SDA2_0>; }; }; - i2c3_pins_a: i2c3 { - pins3 { + i2c3_pins_a: i2c3-pins { + pins-bus { pinmux = <MT6797_GPIO75__FUNC_SDA3_0>, <MT6797_GPIO74__FUNC_SCL3_0>; }; }; - i2c4_pins_a: i2c4 { - pins4 { + i2c4_pins_a: i2c4-pins { + pins-bus { pinmux = <MT6797_GPIO238__FUNC_SDA4_0>, <MT6797_GPIO239__FUNC_SCL4_0>; }; }; - i2c5_pins_a: i2c5 { - pins5 { + i2c5_pins_a: i2c5-pins { + pins-bus { pinmux = <MT6797_GPIO240__FUNC_SDA5_0>, <MT6797_GPIO241__FUNC_SCL5_0>; }; }; - i2c6_pins_a: i2c6 { - pins6 { + i2c6_pins_a: i2c6-pins { + pins-bus { pinmux = <MT6797_GPIO152__FUNC_SDA6_0>, <MT6797_GPIO151__FUNC_SCL6_0>; }; }; - i2c7_pins_a: i2c7 { - pins7 { + i2c7_pins_a: i2c7-pins { + pins-bus { pinmux = <MT6797_GPIO154__FUNC_SDA7_0>, <MT6797_GPIO153__FUNC_SCL7_0>; }; @@ -228,7 +228,7 @@ #clock-cells = <1>; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; @@ -285,7 +285,6 @@ i2c0: i2c@11007000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <0>; reg = <0 0x11007000 0 0x1000>, <0 0x11000100 0 0x80>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; @@ -301,7 +300,6 @@ i2c1: i2c@11008000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <1>; reg = <0 0x11008000 0 0x1000>, <0 0x11000180 0 0x80>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; @@ -317,7 +315,6 @@ i2c8: i2c@11009000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <8>; reg = <0 0x11009000 0 0x1000>, <0 0x11000200 0 0x80>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; @@ -334,7 +331,6 @@ i2c9: i2c@1100d000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <9>; reg = <0 0x1100d000 0 0x1000>, <0 0x11000280 0 0x80>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; @@ -351,7 +347,6 @@ i2c6: i2c@1100e000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <6>; reg = <0 0x1100e000 0 0x1000>, <0 0x11000500 0 0x80>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; @@ -367,7 +362,6 @@ i2c7: i2c@11010000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <7>; reg = <0 0x11010000 0 0x1000>, <0 0x11000580 0 0x80>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; @@ -383,7 +377,6 @@ i2c4: i2c@11011000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <4>; reg = <0 0x11011000 0 0x1000>, <0 0x11000300 0 0x80>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; @@ -399,7 +392,6 @@ i2c2: i2c@11013000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <2>; reg = <0 0x11013000 0 0x1000>, <0 0x11000400 0 0x80>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; @@ -416,7 +408,6 @@ i2c3: i2c@11014000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <3>; reg = <0 0x11014000 0 0x1000>, <0 0x11000480 0 0x80>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; @@ -433,7 +424,6 @@ i2c5: i2c@1101c000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <5>; reg = <0 0x1101c000 0 0x1000>, <0 0x11000380 0 0x80>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts index 08b3b0827436..30805a610262 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts @@ -98,8 +98,6 @@ flash@0 { compatible = "spi-nand"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <52000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index ed79ad1ae871..e7654dc9a1c9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -64,23 +64,19 @@ }; /* i2c of the left SFP cage (wan) */ - i2c_sfp1: i2c-gpio-0 { + i2c_sfp1: i2c-0 { compatible = "i2c-gpio"; sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; }; /* i2c of the right SFP cage (lan) */ - i2c_sfp2: i2c-gpio-1 { + i2c_sfp2: i2c-1 { compatible = "i2c-gpio"; sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; }; leds { @@ -204,8 +200,9 @@ compatible = "mediatek,mt7531"; reg = <31>; interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; - interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>; reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index a9e079fd42c6..a8972330a7b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -428,16 +428,16 @@ }; }; - pcie_phy: t-phy { + pcie_phy: t-phy@11c00000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; - ranges; - #address-cells = <2>; - #size-cells = <2>; + ranges = <0 0 0x11c00000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; status = "disabled"; - pcie_port: pcie-phy@11c00000 { - reg = <0 0x11c00000 0 0x20000>; + pcie_port: pcie-phy@0 { + reg = <0 0x20000>; clocks = <&clk40m>; clock-names = "ref"; #phy-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi index 586eee79c73c..f69ffcb9792a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi @@ -39,8 +39,8 @@ }; &pio { - da7219_pins: da7219_pins { - pins1 { + da7219_pins: da7219-pins { + pins-intn { pinmux = <PINMUX_GPIO165__FUNC_GPIO165>; input-enable; bias-pull-up; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi index 548e22c194a2..c4aedf8cbfcd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi @@ -17,7 +17,7 @@ }; &pio { - ts3a227e_pins: ts3a227e_pins { + ts3a227e_pins: ts3a227e-pins { pins1 { pinmux = <PINMUX_GPIO157__FUNC_GPIO157>; input-enable; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 80888bd4ad82..1b74ec171c10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -93,11 +93,6 @@ }; }; -&dsi0 { - status = "okay"; - /delete-node/panel@0; -}; - &dsi_out { remote-endpoint = <&anx7625_in>; }; @@ -395,14 +390,14 @@ "", ""; - pp1000_mipibrdg_en: pp1000-mipibrdg-en { + pp1000_mipibrdg_en: pp1000-mipibrdg-en-pins { pins1 { pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; output-low; }; }; - pp1800_mipibrdg_en: pp1800-mipibrdg-en { + pp1800_mipibrdg_en: pp1800-mipibrdg-en-pins { pins1 { pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; output-low; @@ -410,20 +405,20 @@ }; pp3300_panel_pins: pp3300-panel-pins { - panel_3v3_enable: panel-3v3-enable { + panel_3v3_enable: pins-panel-en { pinmux = <PINMUX_GPIO35__FUNC_GPIO35>; output-low; }; }; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; output-low; @@ -444,27 +439,27 @@ }; touchscreen_pins: touchscreen-pins { - touch-int-odl { + pins-intn { pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; input-enable; bias-pull-up; }; - touch-rst-l { + pins-rst { pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; output-high; }; }; trackpad_pins: trackpad-pins { - trackpad-int { + pins-intn { pinmux = <PINMUX_GPIO7__FUNC_GPIO7>; input-enable; bias-disable; /* pulled externally */ }; }; - pp3300_mipibrdg_en: pp3300-mipibrdg-en { + pp3300_mipibrdg_en: pp3300-mipibrdg-en-pins { pins1 { pinmux = <PINMUX_GPIO37__FUNC_GPIO37>; output-low; @@ -472,13 +467,13 @@ }; volume_button_pins: volume-button-pins { - voldn-btn-odl { + pins-voldn { pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; input-enable; bias-pull-up; }; - volup-btn-odl { + pins-volup { pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; input-enable; bias-pull-up; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi index ff02f63bac29..d71972c94e42 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -61,6 +61,33 @@ firmware-name = "nvm_00440302_i2s_eu.bin"; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; }; @@ -304,35 +331,35 @@ "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; output-low; }; }; - open_touch: open_touch { - irq_pin { + open_touch: opentouch-pins { + pins-intn { pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; input-enable; bias-pull-up; }; - rst_pin { + pins-rst { pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; /* @@ -349,8 +376,8 @@ }; }; - pen_eject: peneject { - pen_eject { + pen_eject: pen-pins { + pins-eject { pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; input-enable; /* External pull-up. */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index da6e767b4cee..b702ff066636 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -42,6 +42,34 @@ }; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; @@ -292,35 +320,35 @@ "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; output-low; }; }; - touch_default: touchdefault { - pin_irq { + touch_default: touch-pins { + pins-intn { pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; input-enable; bias-pull-up; }; - touch_pin_reset: pin_reset { + touch_pin_reset: pins-rst { pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; /* diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi index 8b56b8564ed7..b6cfcafd8b06 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -45,6 +45,34 @@ firmware-name = "nvm_00440302_i2s_eu.bin"; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; @@ -296,35 +324,35 @@ "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; output-low; }; }; - open_touch: open_touch { - irq_pin { + open_touch: opentouch-pins { + pins-intn { pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; input-enable; bias-pull-up; }; - rst_pin { + pins-rst { pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; /* diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index fff93e26eb76..4b87d4940c8c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -252,29 +252,6 @@ &dsi0 { status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - panel: panel@0 { - /* compatible will be set in board dts */ - reg = <0>; - enable-gpios = <&pio 45 0>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_pins_default>; - avdd-supply = <&ppvarn_lcd>; - avee-supply = <&ppvarp_lcd>; - pp1800-supply = <&pp1800_lcd>; - backlight = <&backlight_lcd0>; - rotation = <270>; - port { - panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&dsi_out { - remote-endpoint = <&panel_in>; }; &gic { @@ -435,7 +412,7 @@ }; &pio { - aud_pins_default: audiopins { + aud_pins_default: audio-pins { pins-bus { pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, <PINMUX_GPIO98__FUNC_I2S2_BCK>, @@ -457,7 +434,7 @@ }; }; - aud_pins_tdm_out_on: audiotdmouton { + aud_pins_tdm_out_on: audio-tdmout-on-pins { pins-bus { pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, @@ -469,7 +446,7 @@ }; }; - aud_pins_tdm_out_off: audiotdmoutoff { + aud_pins_tdm_out_off: audio-tdmout-off-pins { pins-bus { pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, <PINMUX_GPIO170__FUNC_GPIO170>, @@ -490,22 +467,22 @@ }; }; - ec_ap_int_odl: ec-ap-int-odl { - pins1 { + ec_ap_int_odl: ec-ap-int-odl-pins { + pins-intn { pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; input-enable; bias-pull-up; }; }; - h1_int_od_l: h1-int-od-l { - pins1 { + h1_int_od_l: h1-int-od-l-pins { + pins-intn { pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; input-enable; }; }; - i2c0_pins: i2c0 { + i2c0_pins: i2c0-pins { pins-bus { pinmux = <PINMUX_GPIO82__FUNC_SDA0>, <PINMUX_GPIO83__FUNC_SCL0>; @@ -513,7 +490,7 @@ }; }; - i2c1_pins: i2c1 { + i2c1_pins: i2c1-pins { pins-bus { pinmux = <PINMUX_GPIO81__FUNC_SDA1>, <PINMUX_GPIO84__FUNC_SCL1>; @@ -521,7 +498,7 @@ }; }; - i2c2_pins: i2c2 { + i2c2_pins: i2c2-pins { pins-bus { pinmux = <PINMUX_GPIO103__FUNC_SCL2>, <PINMUX_GPIO104__FUNC_SDA2>; @@ -529,7 +506,7 @@ }; }; - i2c3_pins: i2c3 { + i2c3_pins: i2c3-pins { pins-bus { pinmux = <PINMUX_GPIO50__FUNC_SCL3>, <PINMUX_GPIO51__FUNC_SDA3>; @@ -537,7 +514,7 @@ }; }; - i2c4_pins: i2c4 { + i2c4_pins: i2c4-pins { pins-bus { pinmux = <PINMUX_GPIO105__FUNC_SCL4>, <PINMUX_GPIO106__FUNC_SDA4>; @@ -545,7 +522,7 @@ }; }; - i2c5_pins: i2c5 { + i2c5_pins: i2c5-pins { pins-bus { pinmux = <PINMUX_GPIO48__FUNC_SCL5>, <PINMUX_GPIO49__FUNC_SDA5>; @@ -553,7 +530,7 @@ }; }; - i2c6_pins: i2c6 { + i2c6_pins: i2c6-pins { pins-bus { pinmux = <PINMUX_GPIO11__FUNC_SCL6>, <PINMUX_GPIO12__FUNC_SDA6>; @@ -561,7 +538,7 @@ }; }; - mmc0_pins_default: mmc0-pins-default { + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, @@ -625,7 +602,7 @@ }; }; - mmc1_pins_default: mmc1-pins-default { + mmc1_pins_default: mmc1-default-pins { pins-cmd-dat { pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, @@ -643,7 +620,7 @@ }; }; - mmc1_pins_uhs: mmc1-pins-uhs { + mmc1_pins_uhs: mmc1-uhs-pins { pins-cmd-dat { pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, @@ -663,15 +640,15 @@ }; }; - panel_pins_default: panel-pins-default { - panel-reset { + panel_pins_default: panel-pins { + pins-panel-reset { pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; output-low; bias-pull-up; }; }; - pwm0_pin_default: pwm0-pin-default { + pwm0_pin_default: pwm0-pins { pins1 { pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; output-high; @@ -682,15 +659,15 @@ }; }; - scp_pins: scp { + scp_pins: scp-pins { pins-scp-uart { pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; }; }; - spi0_pins: spi0 { - pins-spi { + spi0_pins: spi0-pins { + pins-bus { pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, <PINMUX_GPIO86__FUNC_GPIO86>, <PINMUX_GPIO87__FUNC_SPI0_MO>, @@ -699,8 +676,8 @@ }; }; - spi1_pins: spi1 { - pins-spi { + spi1_pins: spi1-pins { + pins-bus { pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, <PINMUX_GPIO163__FUNC_SPI1_A_MO>, @@ -709,21 +686,21 @@ }; }; - spi2_pins: spi2 { - pins-spi { + spi2_pins: spi2-pins { + pins-bus { pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, <PINMUX_GPIO1__FUNC_SPI2_MO>, <PINMUX_GPIO2__FUNC_SPI2_CLK>; bias-disable; }; - pins-spi-mi { + pins-miso { pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; mediatek,pull-down-adv = <00>; }; }; - spi3_pins: spi3 { - pins-spi { + spi3_pins: spi3-pins { + pins-bus { pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, <PINMUX_GPIO22__FUNC_SPI3_CSB>, <PINMUX_GPIO23__FUNC_SPI3_MO>, @@ -732,8 +709,8 @@ }; }; - spi4_pins: spi4 { - pins-spi { + spi4_pins: spi4-pins { + pins-bus { pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, <PINMUX_GPIO18__FUNC_SPI4_CSB>, <PINMUX_GPIO19__FUNC_SPI4_MO>, @@ -742,8 +719,8 @@ }; }; - spi5_pins: spi5 { - pins-spi { + spi5_pins: spi5-pins { + pins-bus { pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, <PINMUX_GPIO14__FUNC_SPI5_CSB>, <PINMUX_GPIO15__FUNC_SPI5_MO>, @@ -752,7 +729,7 @@ }; }; - uart0_pins_default: uart0-pins-default { + uart0_pins_default: uart0-pins { pins-rx { pinmux = <PINMUX_GPIO95__FUNC_URXD0>; input-enable; @@ -763,7 +740,7 @@ }; }; - uart1_pins_default: uart1-pins-default { + uart1_pins_default: uart1-pins { pins-rx { pinmux = <PINMUX_GPIO121__FUNC_URXD1>; input-enable; @@ -781,7 +758,7 @@ }; }; - uart1_pins_sleep: uart1-pins-sleep { + uart1_pins_sleep: uart1-sleep-pins { pins-rx { pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; input-enable; @@ -799,14 +776,14 @@ }; }; - wifi_pins_pwrseq: wifi-pins-pwrseq { + wifi_pins_pwrseq: wifi-pwr-pins { pins-wifi-enable { pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; output-low; }; }; - wifi_pins_wakeup: wifi-pins-wakeup { + wifi_pins_wakeup: wifi-wake-pins { pins-wifi-wakeup { pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; input-enable; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 7c3010889ae7..f60ef3e53a09 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -482,6 +482,10 @@ domain-supply = <&mt6358_vgpu_reg>; }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; @@ -527,10 +531,8 @@ pinctrl-0 = <&dpi_func_pins>; pinctrl-1 = <&dpi_idle_pins>; status = "okay"; +}; - port { - dpi_out: endpoint { - remote-endpoint = <&it66121_in>; - }; - }; +&dpi_out { + remote-endpoint = <&it66121_in>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 3c1fe80e64b9..960d8955d018 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1667,6 +1667,21 @@ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + + mmsys_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&ovl_2l1_in>; + }; + }; }; dma-controller0@14001000 { @@ -1733,6 +1748,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&mmsys_ep_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&ovl_2l0_in>; + }; + }; + }; }; ovl_2l0: ovl@14009000 { @@ -1743,6 +1777,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl_2l0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + ovl_2l0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; ovl_2l1: ovl@1400a000 { @@ -1753,6 +1806,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl_2l1_in: endpoint { + remote-endpoint = <&mmsys_ep_ext>; + }; + }; + + port@1 { + reg = <1>; + ovl_2l1_out: endpoint { + remote-endpoint = <&rdma1_in>; + }; + }; + }; }; rdma0: rdma@1400b000 { @@ -1764,6 +1836,25 @@ iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl_2l0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; rdma1: rdma@1400c000 { @@ -1775,6 +1866,25 @@ iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma1_in: endpoint { + remote-endpoint = <&ovl_2l1_out>; + }; + }; + + port@1 { + reg = <1>; + rdma1_out: endpoint { + remote-endpoint = <&dpi_in>; + }; + }; + }; }; color0: color@1400e000 { @@ -1785,6 +1895,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1400f000 { @@ -1794,6 +1923,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@14010000 { @@ -1803,6 +1951,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@14011000 { @@ -1812,6 +1979,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@14012000 { @@ -1821,6 +2007,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; }; dsi0: dsi@14014000 { @@ -1837,8 +2042,21 @@ phy-names = "dphy"; status = "disabled"; - port { - dsi_out: endpoint { }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { }; + }; }; }; @@ -1853,8 +2071,21 @@ clock-names = "pixel", "engine", "pll"; status = "disabled"; - port { - dpi_out: endpoint { }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi_in: endpoint { + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + reg = <1>; + dpi_out: endpoint { }; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi index 7c971198fa95..72a2a2bff0a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi @@ -71,14 +71,14 @@ i2c-scl-internal-delay-ns = <10000>; touchscreen: touchscreen@10 { - compatible = "hid-over-i2c"; + compatible = "elan,ekth6915"; reg = <0x10>; interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; - vdd-supply = <&pp3300_s3>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vcc33-supply = <&pp3300_s3>; + no-reset-on-power-off; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts index 26d3451a5e47..24d9ede63eaa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts @@ -42,3 +42,7 @@ CROS_STD_MAIN_KEYMAP >; }; + +&touchscreen { + compatible = "elan,ekth6a12nay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index c5254ae0bb99..7fedbacdac44 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -164,6 +164,12 @@ #size-cells = <2>; ranges; + scp_mem_reserved: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x800000>; + no-map; + }; + apu_mem: memory@55000000 { compatible = "shared-dma-pool"; reg = <0 0x55000000 0 0x1400000>; @@ -1077,6 +1083,13 @@ }; }; + scp_pins: scp-pins { + pins-scp-vreq { + pinmux = <PINMUX_GPIO98__FUNC_O_SCP_VREQ_VAO>; + bias-disable; + }; + }; + spi0_pins: spi0-pins { pins-bus { pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, @@ -1146,6 +1159,18 @@ remote-endpoint = <&dither0_in>; }; +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + firmware-name = "mediatek/mt8188/scp.img"; + memory-region = <&scp_mem_reserved>; + status = "okay"; +}; + &sound { pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", "aud_etdm_spk_on", "aud_etdm_spk_off", diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 202478407727..90c388f1890f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2183,7 +2183,7 @@ }; efuse: efuse@11f20000 { - compatible = "mediatek,mt8188-efuse", "mediatek,efuse"; + compatible = "mediatek,mt8188-efuse", "mediatek,mt8186-efuse"; reg = <0 0x11f20000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts index a82d716f10d4..a50b4e8efaba 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts @@ -13,6 +13,7 @@ &audio_codec { compatible = "realtek,rt5682i"; realtek,btndet-delay = <16>; + VBAT-supply = <&pp3300_z5>; }; &sound { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts index 2d6522c144b7..a8657c0068d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -13,6 +13,7 @@ &audio_codec { compatible = "realtek,rt5682i"; realtek,btndet-delay = <16>; + VBAT-supply = <&pp3300_z5>; }; &pio_default { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index e70599807bb1..b3761b80cac7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -534,8 +534,9 @@ realtek,jd-src = <1>; AVDD-supply = <&mt6359_vio18_ldo_reg>; + DBVDD-supply = <&mt6359_vio18_ldo_reg>; MICVDD-supply = <&pp3300_z2>; - VBAT-supply = <&pp3300_z5>; + LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index ab0b2f606eb4..ec452d657031 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3036,7 +3036,7 @@ #size-cells = <2>; }; - jpgdec-master { + jpeg-decoder@1a040000 { compatible = "mediatek,mt8195-jpgdec"; power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, @@ -3047,11 +3047,12 @@ <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0 0 0 0x1a040000 0 0x20000>, + <1 0 0 0x1b040000 0 0x10000>; - jpgdec@1a040000 { + jpgdec@0,0 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ + reg = <0 0 0 0x10000>;/* JPGDEC_C0 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, @@ -3064,9 +3065,9 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; }; - jpgdec@1a050000 { + jpgdec@0,10000 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ + reg = <0 0 0x10000 0x10000>;/* JPGDEC_C1 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, @@ -3079,9 +3080,9 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; }; - jpgdec@1b040000 { + jpgdec@1,0 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ + reg = <1 0 0 0x10000>;/* JPGDEC_C2 */ iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, @@ -3110,7 +3111,7 @@ }; - jpgenc-master { + jpeg-encoder@1a030000 { compatible = "mediatek,mt8195-jpgenc"; power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, @@ -3119,11 +3120,12 @@ <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0 0 0 0x1a030000 0 0x10000>, + <1 0 0 0x1b030000 0 0x10000>; - jpgenc@1a030000 { + jpgenc@0,0 { compatible = "mediatek,mt8195-jpgenc-hw"; - reg = <0 0x1a030000 0 0x10000>; + reg = <0 0 0 0x10000>; iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, @@ -3134,9 +3136,9 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; - jpgenc@1b030000 { + jpgenc@1,0 { compatible = "mediatek,mt8195-jpgenc-hw"; - reg = <0 0x1b030000 0 0x10000>; + reg = <1 0 0 0x10000>; iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts index 4985b65925a9..d16f545cbbb2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts @@ -352,7 +352,7 @@ LDO_VIN2-supply = <&vsys>; LDO_VIN3-supply = <&vsys>; - mt6360_buck1: BUCK1 { + mt6360_buck1: buck1 { regulator-name = "emi_vdd2"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1800000>; @@ -362,7 +362,7 @@ regulator-always-on; }; - mt6360_buck2: BUCK2 { + mt6360_buck2: buck2 { regulator-name = "emi_vddq"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1300000>; @@ -372,7 +372,7 @@ regulator-always-on; }; - mt6360_ldo1: LDO1 { + mt6360_ldo1: ldo1 { regulator-name = "mt6360_ldo1"; /* Test point */ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; @@ -380,7 +380,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo2: LDO2 { + mt6360_ldo2: ldo2 { regulator-name = "panel1_p1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -388,7 +388,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo3: LDO3 { + mt6360_ldo3: ldo3 { regulator-name = "vmc_pmu"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -396,7 +396,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo5: LDO5 { + mt6360_ldo5: ldo5 { regulator-name = "vmch_pmu"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -404,7 +404,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo6: LDO6 { + mt6360_ldo6: ldo6 { regulator-name = "mt6360_ldo6"; /* Test point */ regulator-min-microvolt = <500000>; regulator-max-microvolt = <2100000>; @@ -412,7 +412,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo7: LDO7 { + mt6360_ldo7: ldo7 { regulator-name = "emi_vmddr_en"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts index cce642c53812..3d3db33a64dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts @@ -11,7 +11,7 @@ / { model = "Pumpkin MT8516"; - compatible = "mediatek,mt8516"; + compatible = "mediatek,mt8516-pumpkin", "mediatek,mt8516"; memory@40000000 { device_type = "memory"; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index a356db5fcc5f..805fb82138a8 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -198,8 +198,8 @@ }; &pio { - gpio_keys_default: gpiodefault { - pins_cmd_dat { + gpio_keys_default: gpio-keys-pins { + pins-cmd-dat { pinmux = <MT8516_PIN_42_KPCOL0__FUNC_GPIO42>, <MT8516_PIN_43_KPCOL1__FUNC_GPIO43>; bias-pull-up; @@ -207,7 +207,7 @@ }; }; - i2c0_pins_a: i2c0 { + i2c0_pins_a: i2c0-pins { pins1 { pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>, <MT8516_PIN_59_SCL0__FUNC_SCL0_0>; @@ -215,7 +215,7 @@ }; }; - i2c2_pins_a: i2c2 { + i2c2_pins_a: i2c2-pins { pins1 { pinmux = <MT8516_PIN_60_SDA2__FUNC_SDA2_0>, <MT8516_PIN_61_SCL2__FUNC_SCL2_0>; @@ -223,21 +223,21 @@ }; }; - tca6416_pins: pinmux_tca6416_pins { - gpio_mux_rst_n_pin { + tca6416_pins: tca6416-pins { + pins-mux-rstn { pinmux = <MT8516_PIN_65_UTXD1__FUNC_GPIO65>; output-high; }; - gpio_mux_int_n_pin { + pins-mux-intn { pinmux = <MT8516_PIN_64_URXD1__FUNC_GPIO64>; input-enable; bias-pull-up; }; }; - ethernet_pins_default: ethernet { - pins_ethernet { + ethernet_pins_default: ethernet-pins { + pins-eth { pinmux = <MT8516_PIN_0_EINT0__FUNC_EXT_TXD0>, <MT8516_PIN_1_EINT1__FUNC_EXT_TXD1>, <MT8516_PIN_5_EINT5__FUNC_EXT_RXER>, |