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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-08-04 21:26:42 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-08-11 15:47:03 +0200
commit8a5a0294f40a50e5be83e9b7ebbc15b546f64e41 (patch)
tree4f3a5c7e1a3d8bfb07851a2b3cbefdf3f19e037a
parent8f5ae30d69d7543eee0d70083daf4de8fe15d585 (diff)
dt-bindings: clock: renesas,r9a09g077/87: Add USB_CLK clock ID
Add the USB clock (USB_CLK) definition for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. USB_CLK is used as the reference clock for USB PHY layer. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250804202643.3967484-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r--include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h1
-rw-r--r--include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
index 7ecc4f0b235a..0c2ce81a8744 100644
--- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -25,5 +25,6 @@
#define R9A09G077_CLK_PCLKM 13
#define R9A09G077_CLK_PCLKL 14
#define R9A09G077_SDHI_CLKHS 15
+#define R9A09G077_USB_CLK 16
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
index 925e57703925..70ee883f2386 100644
--- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -25,5 +25,6 @@
#define R9A09G087_CLK_PCLKM 13
#define R9A09G087_CLK_PCLKL 14
#define R9A09G087_SDHI_CLKHS 15
+#define R9A09G087_USB_CLK 16
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */