diff options
| author | Jagan Teki <jagan@edgeble.ai> | 2023-11-26 00:35:18 +0530 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2024-01-25 21:28:47 +0100 |
| commit | 8c711ff32748b46688ddc6663e377dba12ed22cd (patch) | |
| tree | 283ee89bfb9e3eb9a684f5fdd85c00e6321e0e2c | |
| parent | 9f6d8911cc3b7fbe270ef991b0db0a8b623e01a9 (diff) | |
arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH
Edgeble NCM6A-IO board has 2.5Gbps Ethernet via PCI2_0.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20231125190522.87607-7-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index fb32847a8f8c..65207c7b1bb8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -3,16 +3,31 @@ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. */ +#include <dt-bindings/gpio/gpio.h> + / { chosen { stdout-path = "serial2:1500000n8"; }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; }; &combphy0_ps { status = "okay"; }; +&combphy1_ps { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -29,7 +44,22 @@ }; }; +/* ETH */ +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */ + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + &pinctrl { + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; |