diff options
| author | Samuel Holland <samuel.holland@sifive.com> | 2025-09-09 15:41:27 -0700 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-09-11 19:13:21 +0100 |
| commit | 941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0 (patch) | |
| tree | 5de5229522d713a39c0d385d2148f28eb2f0f644 | |
| parent | 4fab69dd1fa52e28bb692afcb159fa8807d6d03f (diff) | |
cache: sifive_ccache: Optimize cache flushes
Fence instructions are required only at the beginning and the end of
a flush operation, not separately for each cache line being flushed.
Speed up cache flushes by about 15% by removing the extra fences.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | drivers/cache/sifive_ccache.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index e1a283805ea7..a86800b123b9 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -151,16 +151,16 @@ static void ccache_flush_range(phys_addr_t start, size_t len) if (!len) return; - mb(); + mb(); /* complete earlier memory accesses before the cache flush */ for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end; line += SIFIVE_CCACHE_LINE_SIZE) { #ifdef CONFIG_32BIT - writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); + writel_relaxed(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); #else - writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64); + writeq_relaxed(line, ccache_base + SIFIVE_CCACHE_FLUSH64); #endif - mb(); } + mb(); /* issue later memory accesses after the cache flush */ } static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = { |