diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2025-01-25 18:51:33 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2025-01-25 18:51:33 +0800 |
| commit | 98e720f77dba6bb702a57f3d8479e6445e34f38c (patch) | |
| tree | 09e72d98a3a749f0400e88f5f3949f1c4d514d61 | |
| parent | 341cf992d331a34d764bf943e4e177daff94fc92 (diff) | |
LoongArch: Derive timer max_delta from PRCFG1's timer_bits
As per arch spec, maximum timer bits is configurable and should not be
hardcoded in any way.
Probe timer bits from PRCFG1 and use that to determine the clockevent's
max_delta to be conformance.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
| -rw-r--r-- | arch/loongarch/include/asm/cpu-info.h | 1 | ||||
| -rw-r--r-- | arch/loongarch/include/asm/loongarch.h | 1 | ||||
| -rw-r--r-- | arch/loongarch/kernel/cpu-probe.c | 1 | ||||
| -rw-r--r-- | arch/loongarch/kernel/time.c | 2 |
4 files changed, 3 insertions, 2 deletions
diff --git a/arch/loongarch/include/asm/cpu-info.h b/arch/loongarch/include/asm/cpu-info.h index 900589cb159d..35e0a230a484 100644 --- a/arch/loongarch/include/asm/cpu-info.h +++ b/arch/loongarch/include/asm/cpu-info.h @@ -57,6 +57,7 @@ struct cpuinfo_loongarch { int global_id; /* physical global thread number */ int vabits; /* Virtual Address size in bits */ int pabits; /* Physical Address size in bits */ + int timerbits; /* Width of arch timer in bits */ unsigned int ksave_mask; /* Usable KSave mask. */ unsigned int watch_dreg_count; /* Number data breakpoints */ unsigned int watch_ireg_count; /* Number instruction breakpoints */ diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h index 64ad277e096e..a3cc4f8d4c4a 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -466,7 +466,6 @@ #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ #define CSR_TCFG_VAL_SHIFT 2 -#define CSR_TCFG_VAL_WIDTH 48 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT) #define CSR_TCFG_PERIOD_SHIFT 1 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT) diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c index cbce099037b2..fedaa67cde41 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -190,6 +190,7 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c) set_cpu_asid_mask(c, asid_mask); config = read_csr_prcfg1(); + c->timerbits = (config & CSR_CONF1_TMRBITS) >> CSR_CONF1_TMRBITS_SHIFT; c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0); c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK); diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c index a07d7eff4dc5..e2d3bfeb6366 100644 --- a/arch/loongarch/kernel/time.c +++ b/arch/loongarch/kernel/time.c @@ -132,7 +132,7 @@ int constant_clockevent_init(void) #else unsigned long min_delta = 1000; #endif - unsigned long max_delta = (1UL << 48) - 1; + unsigned long max_delta = GENMASK_ULL(boot_cpu_data.timerbits, 0); struct clock_event_device *cd; static int irq = 0, timer_irq_installed = 0; |