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| author | Stephen Boyd <sboyd@kernel.org> | 2025-07-21 17:20:15 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-07-21 17:20:15 -0700 |
| commit | a0a6f598e34312793c75bf1a63eeb9c4bd572427 (patch) | |
| tree | 1e97ced4455cc0ee0b79556da6087d2979a0a23a | |
| parent | 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 (diff) | |
| parent | 132b62280a9dbe38c627183ae7f1611de3ee0d9a (diff) | |
Merge tag 'v6.17-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull a Rockchip clk driver update from Heiko Stuebner:
- 132MHz PLL rate for Rockchip rk3588
* tag 'v6.17-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3568: Add PLL rate for 132MHz
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3568.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index d48ab9d6c064..97d279399ae8 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), + RK3036_PLL_RATE(132000000, 1, 66, 6, 2, 1, 0), RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0), RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0), RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), |