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authorAkhil P Oommen <akhilpo@oss.qualcomm.com>2025-09-08 13:57:05 +0530
committerRob Clark <robin.clark@oss.qualcomm.com>2025-09-08 07:25:00 -0700
commita242ef4a7577bfd3dbf0b4fb7bf92adca145b0c1 (patch)
tree3284eb53331a69da83f9f2c0a7ae5004852294cc
parent365075b7d0b95c737284d6970769e964c7e7052d (diff)
drm/msm/a6xx: Fix hangcheck for IFPC
From the hangcheck handler, KMD checks a few registers in GX domain to see if the GPU made any progress. But it cannot access those registers when IFPC is enabled. Since HW based hang detection is pretty decent, lets rely on it instead of these registers when IFPC is enabled. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673378/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gpu.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 4cdbad05affc..b6b68b555a0e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2420,13 +2420,24 @@ static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{
- struct msm_cp_state cp_state = {
+ struct msm_cp_state cp_state;
+ bool progress;
+
+ /*
+ * With IFPC, KMD doesn't know whether GX power domain is collapsed
+ * or not. So, we can't blindly read the below registers in GX domain.
+ * Lets trust the hang detection in HW and lie to the caller that
+ * there was progress.
+ */
+ if (to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC)
+ return true;
+
+ cp_state = (struct msm_cp_state) {
.ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE),
.ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE),
.ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
.ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE),
};
- bool progress;
/*
* Adjust the remaining data to account for what has already been