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authorCyan Yang <cyan.yang@sifive.com>2025-04-18 13:32:38 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2025-05-08 11:01:44 -0700
commita3ca43dc527159aa6f55058a9fa506fa720d6514 (patch)
tree6559b92cb480d96fa43f1efcdd0b407002bfa02b
parent34e9b16b4b888988730ffab9a9039cfcf305942e (diff)
riscv: hwprobe: Document SiFive xsfvfwmaccqqq vendor extension
Document the support for matrix multiply accumulate instruction from SiFive using RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ. Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-12-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
-rw-r--r--Documentation/arch/riscv/hwprobe.rst4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index e15405e12239..7c11351b1383 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -353,3 +353,7 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
Clip Instructions Extensions Specification.
+
+ * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
+ vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
+ Instruction Extensions Specification. \ No newline at end of file