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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-19 20:11:28 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-19 20:11:28 +0200 |
| commit | a9f57b8d5f0546bbc49448370995696ec9dcb83e (patch) | |
| tree | 1b591372adaf754865e71ace0b0395896830fd51 | |
| parent | c939b63f44e50c3d2bd3790cddf07c3ef805ca5f (diff) | |
| parent | 62ab7ac5be90392a9ac0955febab778ebf51bc0a (diff) | |
Merge tag 'renesas-r9a09g077-dt-binding-defs-tag2' into renesas-clk-for-v6.17
Renesas RZ/T2H PCLKL Clock DT Binding Definition
Peripheral Module Clock L (PCLKL) DT binding definition for the Renesas
RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 1b22fe88dec7..f6e5f62b07c4 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -23,5 +23,6 @@ #define R9A09G077_CLK_PCLKGPTL 11 #define R9A09G077_CLK_PCLKH 12 #define R9A09G077_CLK_PCLKM 13 +#define R9A09G077_CLK_PCLKL 14 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ |