diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2019-04-19 13:20:58 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-19 13:20:58 -0700 |
| commit | aa2a0592ceb65bcba5fa1b8d9a7fb8c43d7cadb9 (patch) | |
| tree | 041395168f069b9e5b1cfe7440a4e9e8069cda57 | |
| parent | 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff) | |
| parent | 691dc382769e350d4bc6f90a8edcacf7f8863d70 (diff) | |
Merge tag 'clk-v5.2-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Addition of ADC clock definition for Exynos 5410 SoC (Odroid XU)
* tag 'clk-v5.2-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: exynos5410: Add gate clock for ADC
clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410
clk: samsung: dt-bindings: Put CLK_UART3 in order
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5410.c | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos5410.h | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 0a0b09591e6f..b2da2c8fa0c7 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), + GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0), GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index f179eabbcdb7..86c2ad56c5ef 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -36,6 +36,7 @@ #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 +#define CLK_UART3 260 #define CLK_I2C0 261 #define CLK_I2C1 262 #define CLK_I2C2 263 @@ -44,7 +45,7 @@ #define CLK_USI1 266 #define CLK_USI2 267 #define CLK_USI3 268 -#define CLK_UART3 260 +#define CLK_TSADC 270 #define CLK_PWM 279 #define CLK_MCT 315 #define CLK_WDT 316 |