diff options
| author | Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> | 2024-12-19 23:36:55 +0100 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2025-01-03 07:20:15 -0800 |
| commit | bb5acdeae4088297444db1a197f0c66908ba2e56 (patch) | |
| tree | 50cde4a563d9f9d6889c08e4b69af1d830dcd653 | |
| parent | c5fb51b71788926feef0d07f30c8af1d5e4af1a6 (diff) | |
drm/msm: registers: Add GMU FW version register
Add a register that contains the GMU core firmware version on non-
legacy (non-sdm845-family) SoCs.
The name is guesstimated based on what it does downstream, but it'll
do.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/629932/
Signed-off-by: Rob Clark <robdclark@chromium.org>
| -rw-r--r-- | drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml index 6531749d30f4..3d2cc339b8f1 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml @@ -52,6 +52,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/> <reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/> <reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/> + <reg32 offset="0x2bf8" name="GMU_CORE_FW_VERSION"> + <bitfield name="MAJOR" low="28" high="31"/> + <bitfield name="MINOR" low="16" high="27"/> + <bitfield name="STEP" low="0" high="15"/> + </reg32> <reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/> <reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/> <reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/> |