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authorJerome Brunet <jbrunet@baylibre.com>2025-08-25 16:26:31 +0200
committerJerome Brunet <jbrunet@baylibre.com>2025-09-04 18:27:12 +0200
commitcf03071b7c3f1537dba21a64bcd1559b5201a156 (patch)
tree61ec4da2677e3a6b1c7ded65d52abc47b88f8308
parent32ee5475f7e34fbd6539998a4e5f9bd05486672e (diff)
clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
On Amlogic SoCs, the rate of a peripheral clock should not be changed, let alone the rate of the parent PLL. These clocks are meant to be used as provided by the parent PLL. Changing the rate would be dangerous and would likely break a lot of devices running from the same PLL. Don't propagate any rate change request that may come from these clocks and drop the corresponding flag. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-6-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-rw-r--r--drivers/clk/meson/meson-clkc-utils.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson-clkc-utils.h
index 0c228a6723bb..3e1fb7efe6da 100644
--- a/drivers/clk/meson/meson-clkc-utils.h
+++ b/drivers/clk/meson/meson-clkc-utils.h
@@ -38,7 +38,7 @@ struct clk_regmap _name = { \
.ops = _ops, \
.parent_hws = (const struct clk_hw *[]) { _pname }, \
.num_parents = 1, \
- .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
+ .flags = CLK_IGNORE_UNUSED, \
}, \
}