diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-11-06 17:52:49 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-11-07 20:29:43 +0200 |
| commit | d4270f090d90a3a5b974e7efdefeec2fe6a41232 (patch) | |
| tree | cb015965d3b20186300d807f92328de57714b412 | |
| parent | 2d41de2565ef485c31bebef15b8661b177991016 (diff) | |
drm/i915/cx0: s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_MS/
Include the units the in the define name for XELPDP_PORT_RESET_END_TIMEOUT
to make it match all its other counterparts.
v2: It's _MS not _US (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251106155249.2810-1-ville.syrjala@linux.intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index dd1429fa5028..1551d30ec584 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2926,7 +2926,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder, if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_current_status, - XELPDP_PORT_RESET_END_TIMEOUT)) + XELPDP_PORT_RESET_END_TIMEOUT_MS)) drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n", phy_name(phy)); diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index 715ca004516a..8df5cd5ce418 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -80,7 +80,7 @@ #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 #define XELPDP_PORT_RESET_START_TIMEOUT_US 5 #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS 2 -#define XELPDP_PORT_RESET_END_TIMEOUT 15 +#define XELPDP_PORT_RESET_END_TIMEOUT_MS 15 #define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1 #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004 |