diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-06-10 12:24:14 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-07-04 08:34:03 +0300 |
| commit | d657ab84476b1e11146b0c0fa7856d39a8b80da2 (patch) | |
| tree | 0fd5d8249f9b3327ca73cb6b43e601aee91adc57 | |
| parent | 979813d2ab70513a4dca68a13cd75fc656579b19 (diff) | |
ARM: dts: at91: sama7g5: add reset-controller node
Add reset controller node.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220610092414.1816571-10-claudiu.beznea@microchip.com
| -rw-r--r-- | arch/arm/boot/dts/sama7g5.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index a37e3a80392d..bb6d71e6dfeb 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -198,6 +198,13 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + shdwc: shdwc@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; |