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authorNishanth Menon <nm@ti.com>2024-06-27 11:25:38 -0500
committerVignesh Raghavendra <vigneshr@ti.com>2024-07-01 21:36:07 +0530
commitd72d73a44c3c98109764bfb56c329cd628c518cc (patch)
treed8739208465b4bdf9e25e4fc62fe06cf84de82b3
parent50d9981fa12212cdc0110c42db0411209bb5d765 (diff)
arm64: dts: ti: k3-am62p: Add gpio-ranges properties
On the AM62P platform we have no single 1:1 relation regarding index of GPIO and pin controller. The GPIOs and pin controller registers have mapping and holes in the map. These have been extracted from the AM62P data sheet. MCU pinctrl definition is shared as it is common between AM62P and J722S, but that is not the case for main domain. Ref: AM62P Data sheet https://www.ti.com/lit/gpn/am62p Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20240627162539.691223-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
-rw-r--r--arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi8
-rw-r--r--arch/arm64/boot/dts/ti/k3-am62p-main.dtsi17
2 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
index 1d4e5fc8b4e0..e65db6ce02bf 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
@@ -12,7 +12,15 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
+ pinctrl-single,gpio-range =
+ <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>,
+ <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>,
+ <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>;
bootph-all;
+
+ mcu_pmx_range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
};
mcu_esm: esm@4100000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index f8a7f0cbd327..57383bd2eaeb 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -42,10 +42,27 @@
ti,interrupt-ranges = <5 69 35>;
};
+&main_pmx0 {
+ pinctrl-single,gpio-range =
+ <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 33 92 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
+
+ main_pmx0_range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+};
+
&main_gpio0 {
+ gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
+ <&main_pmx0 70 72 22>;
ti,ngpio = <92>;
};
&main_gpio1 {
+ gpio-ranges = <&main_pmx0 0 94 32>, <&main_pmx0 42 137 5>,
+ <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
ti,ngpio = <52>;
};