diff options
| author | Bo Gan <ganboing@gmail.com> | 2024-08-29 23:16:39 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-01-16 13:43:49 -0800 |
| commit | d7f12857f095ef38523399d47e68787b357232f6 (patch) | |
| tree | 08bf8d5b9ab3853dff41cf28e085fc56c1f60fb2 | |
| parent | ab9f0d04ffa9af09a8b0f44940df47c581f1cd00 (diff) | |
clk: analogbits: Fix incorrect calculation of vco rate delta
In wrpll_configure_for_rate() we try to determine the best PLL
configuration for a target rate. However, in the loop where we try
values of R, we should compare the derived `vco` with `target_vco_rate`.
However, we were in fact comparing it with `target_rate`, which is
actually after Q shift. This is incorrect, and sometimes can result in
suboptimal clock rates. Fix it.
Fixes: 7b9487a9a5c4 ("clk: analogbits: add Wide-Range PLL library")
Signed-off-by: Bo Gan <ganboing@gmail.com>
Link: https://lore.kernel.org/r/20240830061639.2316-1-ganboing@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/analogbits/wrpll-cln28hpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c index 65d422a588e1..9d178afc73bd 100644 --- a/drivers/clk/analogbits/wrpll-cln28hpc.c +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c @@ -292,7 +292,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, vco = vco_pre * f; } - delta = abs(target_rate - vco); + delta = abs(target_vco_rate - vco); if (delta < best_delta) { best_delta = delta; best_r = r; |