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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-04-07 20:16:19 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-04-14 10:48:18 +0200
commitdc7af24bd60bdced496d03473e67ce5eb51236a5 (patch)
tree0e56a34ff162f215fff4febbcfb84ee47da1ec66
parentabc43c0f3c3eaa7470004e4e8a190a57c612a686 (diff)
dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
Add the RZ/V2N (R9A09G056) variant to the existing RZ/V2H(P) System Controller (SYS) binding, as both IPs are very similar. However, they have different SoC IDs, and the RZ/V2N does not have PCIE1 configuration registers, unlike the RZ/V2H(P) SYS IP. To handle these differences, introduce a new compatible string `renesas,r9a09g056-sys`. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r--Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
index e0f7503a9f35..c41dcaea568a 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
@@ -25,6 +25,7 @@ properties:
items:
- enum:
- renesas,r9a09g047-sys # RZ/G3E
+ - renesas,r9a09g056-sys # RZ/V2N
- renesas,r9a09g057-sys # RZ/V2H
reg: