Merge branches 'clk-bindings', 'clk-cleanup', 'clk-renesas', 'clk-thead' and 'clk-spacemit' into clk-next

* clk-bindings:
  dt-bindings: clock: mediatek: Add power-domains property
  dt-bindings: clock: silabs,si5341: Add missing properties
  dt-bindings: clock: adi,axi-clkgen: add clock-output-names property
  dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding
  dt-bindings: clock: Convert silabs,si570 to DT schema
  dt-bindings: clock: Convert silabs,si5341 to DT schema
  dt-bindings: clock: Convert silabs,si514/544 to DT schema

* clk-cleanup:
  clk: tegra: do not overallocate memory for bpmp clocks
  clk: ep93xx: Use int type to store negative error codes
  dt-bindings: clock: st: flexgen: remove deprecated compatibles
  clk: st: flexgen: remove unused compatible
  clk: clk-axi-clkgen: remove unneeded semicolon
  clk: tegra: Remove redundant semicolons
  clk: npcm: select CONFIG_AUXILIARY_BUS
  clk: remove unneeded 'fast_io' parameter in regmap_config

* clk-renesas: (27 commits)
  clk: renesas: r9a09g05[67]: Reduce differences
  clk: renesas: r9a09g047: Add USB3.0 clocks/resets
  clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()
  clk: renesas: r9a09g056: Add clock and reset entries for I3C
  clk: renesas: r9a09g057: Add clock and reset entries for I3C
  dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
  clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks
  clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert()
  clk: renesas: rzv2h: Re-assert reset on deassert timeout
  clk: renesas: rzg2l: Re-assert reset on deassert timeout
  clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()
  dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs
  clk: renesas: r9a09g047: Add GPT clocks and resets
  clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5
  clk: renesas: rzv2h: remove round_rate() in favor of determine_rate()
  clk: renesas: rzg2l: convert from round_rate() to determine_rate()
  clk: renesas: r9a07g04[34]: Use tabs instead of spaces
  clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL
  clk: renesas: r9a07g044: Add MSTOP for RZ/G2L
  clk: renesas: r9a08g045: Add MSTOP for GPIO
  ...

* clk-thead:
  clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL
  clk: thead: support changing DPU pixel clock rate
  clk: thead: add support for enabling/disabling PLLs
  clk: thead: Correct parent for DPU pixel clocks
  clk: thead: th1520-ap: fix parent of padctrl0 clock
  clk: thead: th1520-ap: describe gate clocks with clk_gate

* clk-spacemit:
  clk: spacemit: fix i2s clock
  clk: spacemit: introduce pre-div for ddn clock
  dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock
  clk: spacemit: ccu_pll: convert from round_rate() to determine_rate()
  clk: spacemit: ccu_mix: convert from round_rate() to determine_rate()
  clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate()
  clk: spacemit: fix sspax_clk
  dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA