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authorMatt Roper <matthew.d.roper@intel.com>2025-10-16 19:26:26 -0700
committerLucas De Marchi <lucas.demarchi@intel.com>2025-10-17 15:32:38 -0700
commitf4e9acaa5dd58ea4635a2c4a84d188e2a374b807 (patch)
tree6902bf6dd6feed1eb206dd1591512885ba497f2c
parent1553d6c58870476f29ec0bf43f264094553d1407 (diff)
drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting
Since the hardware load balancing is no longer supported, the programming in RCU_MODE is no longer necessary. Bspec: 60382 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://lore.kernel.org/r/20251016-xe3p-v3-7-3dd173a3097a@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
-rw-r--r--drivers/gpu/drm/xe/xe_hw_engine.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index cba4375525c7..b08a6d42c8ff 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -350,6 +350,13 @@ static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe,
const struct xe_gt *gt,
const struct xe_hw_engine *hwe)
{
+ /*
+ * Xe3p no longer supports load balance mode, so "fixed cslice" mode
+ * is automatic and no RCU_MODE programming is required.
+ */
+ if (GRAPHICS_VER(gt_to_xe(gt)) >= 35)
+ return false;
+
return xe_gt_ccs_mode_enabled(gt) &&
xe_rtp_match_first_render_or_compute(xe, gt, hwe);
}