Merge tag 'riscv-sophgo-dt-for-v6.16' of https://github.com/sophgo/linux into soc/late

RISC-V Devicetrees for v6.16

Sophgo:
Add Pinctrl & SPI support for SG2042 SoC, and
refactor the dts of cv18xx to facilitate adding
support for arm core later (SG200X has two cores,
one is RISC-V and another is ARM64).
Also add initial support for Sophgo SG2044/SRD3-10.
SRD3-10 board bases on Sophgo SG2044 SoC and
initial support includes uart only. This part of
the changes involves some modifications to dts
and bindings.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* tag 'riscv-sophgo-dt-for-v6.16' of https://github.com/sophgo/linux:
  riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
  riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
  dt-bindings: riscv: sophgo: Add SG2044 compatible string
  dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
  dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
  riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
  riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
  riscv: dts: sophgo: Move riscv cpu definition to a separate file
  riscv: dts: sophgo: Move all soc specific device into soc dtsi file
  riscv: sophgo: dts: Add spi controller for SG2042
  riscv: dts: sophgo: sg2042: add pinctrl support

Link: https://lore.kernel.org/r/MA0P287MB22622FA23ECF9B9216735FA0FE9CA@MA0P287MB2262.INDP287.PROD.OUTLOOK.COM
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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