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| author | Borislav Petkov <bp@suse.de> | 2021-10-24 17:14:23 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2021-10-24 17:14:23 +0200 |
| commit | a8da61cee95e627ed3d4274861428013aa9604ea (patch) | |
| tree | 461df197af617959ef1ae135d07ab5bdc9916b05 /drivers/clocksource/arc_timer.c | |
| parent | d25a025201ed98f4b93775e0999a3f2135702106 (diff) | |
| parent | eda9a4f7af6ee47e9e131f20e4f8a41a97379293 (diff) | |
Merge tag 'timers-v5.16-rc1' into timers/core
Pull timers update for v5.16 from Daniel Lezcano:
- Fix redefined macro in the arc timer ()
- Big cleanup for ARM arch timer clocksource in order to set the scene
for ARMv8.6 and provide support for higher frequencies with longer
roll up (Marc Zyngier)
- Make arch dependant the Exynos MCT and Samsung PWM timers (Krzysztof
Kozlowski)
- Select the TIMER_OF option for the timer TI DM (Kees Cook)
Link: https://lore.kernel.org/r/65693aaf-ab94-c9bb-a97b-a2bb77033a54@linaro.org
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/clocksource/arc_timer.c')
| -rw-r--r-- | drivers/clocksource/arc_timer.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c index de93dd1a8c7b..cb18524cc13d 100644 --- a/drivers/clocksource/arc_timer.c +++ b/drivers/clocksource/arc_timer.c @@ -225,7 +225,7 @@ static int __init arc_cs_setup_timer1(struct device_node *node) write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); write_aux_reg(ARC_REG_TIMER1_CNT, 0); - write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); + write_aux_reg(ARC_REG_TIMER1_CTRL, ARC_TIMER_CTRL_NH); sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq); @@ -245,7 +245,7 @@ static void arc_timer_event_setup(unsigned int cycles) write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ - write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); + write_aux_reg(ARC_REG_TIMER0_CTRL, ARC_TIMER_CTRL_IE | ARC_TIMER_CTRL_NH); } @@ -294,7 +294,7 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id) * explicitly clears IP bit * 2. Re-arm interrupt if periodic by writing to IE bit [0] */ - write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); + write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | ARC_TIMER_CTRL_NH); evt->event_handler(evt); |