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| author | Mark Brown <broonie@kernel.org> | 2023-09-26 09:35:54 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-09-26 09:35:54 +0200 |
| commit | da6de6d3ecc1ac37c36ed4c0c4ce5dcd410cddcf (patch) | |
| tree | c748b702e792c38b1e84664cc305d0277ce4bbc4 /drivers/fpga/fpga-mgr.c | |
| parent | 8a771075e50bef5e2a063a9f954b36a33fb7359f (diff) | |
| parent | ecdaa9473019f94e0ad6974a5f69b9be7de137d3 (diff) | |
spi: qup: Allow scaling power domains and
Merge series from Stephan Gerhold <stephan.gerhold@kernkonzept.com>:
Make it possible to scale performance states of the power domain and
interconnect of the SPI QUP controller in relation to the selected SPI
speed / core clock. This is done separately by:
- Parsing the OPP table from the device tree for performance state
votes of the power domain
- Voting for the necessary bandwidth on the interconnect path to DRAM
Diffstat (limited to 'drivers/fpga/fpga-mgr.c')
0 files changed, 0 insertions, 0 deletions