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authorMark Brown <broonie@kernel.org>2023-04-17 20:27:00 +0100
committerMark Brown <broonie@kernel.org>2023-04-17 20:27:00 +0100
commited5a25ac750684269b905e434ea9ffcc86e5e75a (patch)
tree25fd16933abc57acadd1cfb37ac51d110d440c57 /drivers/fpga/machxo2-spi.c
parent2c8606040a808aa01d2d9e4f5b9332e87bb66377 (diff)
parentc0b53f4e545e4c6106aab553eb351138d46211cc (diff)
spi: cadence-quadspi: Fix random issues with Xilinx
Merge series from Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>: Update Xilinx Versal external DMA read logic to fix random issues - Instead of having the fixed timeout, update the read timeout based on the length of the transfer to avoid timeout for larger data size. - While switching between external DMA read and indirect read, disable the SPI before configuration and enable it after configuration as recommended by Octal-SPI Flash Controller specification. Sai Krishna Potthuri (2): spi: cadence-quadspi: Update the read timeout based on the length spi: cadence-quadspi: Disable the SPI before reconfiguring drivers/spi/spi-cadence-quadspi.c | 40 ++++++++++++++++++------------- 1 file changed, 24 insertions(+), 16 deletions(-) -- 2.25.1
Diffstat (limited to 'drivers/fpga/machxo2-spi.c')
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