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| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2025-10-28 10:00:54 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2025-11-20 22:30:17 +0530 |
| commit | 72126e9623e1696ea83c77ef6d0306a6263bdd6b (patch) | |
| tree | 1d9a7a4fe254514d00eb3e829d61f89be2fff151 /drivers/fpga/xilinx-spi.c | |
| parent | 9d3daf9ca3239042c2cf473a76db2a77e6de22c6 (diff) | |
phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode
When making use of the clock provider functionality, the output clock
does normally match the TMDS character rate, which is what the PHY PLL
gets configured to.
However, this is only applicable for default color depth of 8 bpc. For
higher depths, the output clock is further divided by the hardware
according to the formula:
output_clock_rate = tmds_char_rate * 8 / bpc
Since the existence of the clock divider wasn't taken into account when
support for high bpc has been introduced, make the necessary adjustments
to report the correct clock rate.
Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management")
Reported-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-1-ecc642a59d94@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions