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authorPalmer Dabbelt <palmer@rivosinc.com>2025-03-26 15:54:12 -0700
committerPalmer Dabbelt <palmer@rivosinc.com>2025-03-26 15:54:12 -0700
commitdf02351331671abb26788bc13f6d276e26ae068f (patch)
tree4e1f8ee707cf6570f39feb47fc5bb151358ebd34 /drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
parent2014c95afecee3e76ca4a56956a936e23283f05b (diff)
parent74f4bf9d15ad1d6862b828d486ed10ea0e874a23 (diff)
Merge tag 'riscv-mw1-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next
riscv patches for 6.15-rc1 * A bunch of fixes: - We were missing a secondary mmu notifier call when flushing the tlb which is required for IOMMU - Fix ftrace panics by saving the registers as expected by ftrace - Fix a couple of stimecmp usage related to cpu hotplug - Fix a bunch of issues in the misaligned probing handling * Perf improvements: - Introduce support for runtime constant improving perf of d_hash() - Add support for huge pfnmaps to improve tlb utilization - Use Zawrs to improve smp_cond_load8/16() used by the queued spinlocks * Hwprobe additions: - Add support for Zicntr and Zihpm - Add support for Zaamo and Zalrsc - Add support for bfloat16 extensiosn - Add support for Zicbom (only enabling clean and flush, not inval for security reasons) * Misc: - Add a kernel parameter to bypass the misaligned speed probing since we can't rely on Zicclsm * tag 'riscv-mw1-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux: (1585 commits) riscv: Add runtime constant support riscv: Move nop definition to insn-def.h Documentation/kernel-parameters: Add riscv unaligned speed parameters riscv: Add parameter for skipping access speed tests riscv: Fix set up of vector cpu hotplug callback riscv: Fix set up of cpu hotplug callbacks riscv: Change check_unaligned_access_speed_all_cpus to void riscv: Fix check_unaligned_access_all_cpus riscv: Fix riscv_online_cpu_vec riscv: Annotate unaligned access init functions KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM riscv: hwprobe: export Zaamo and Zalrsc extensions riscv: add parsing for Zaamo and Zalrsc extensions dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of ftrace_return_to_handler riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on HAVE_DYNAMIC_FTRACE_WITH_ARGS riscv: Fix missing __free_pages() in check_vector_unaligned_access() riscv: Fix the __riscv_copy_vec_words_unaligned implementation riscv: mm: Don't use %pK through printk ...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d100bb7a137c..018dfccd771b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1638,6 +1638,13 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
return 0;
+ /* resizing on Dell G5 SE platforms causes problems with runtime pm */
+ if ((amdgpu_runtime_pm != 0) &&
+ adev->pdev->vendor == PCI_VENDOR_ID_ATI &&
+ adev->pdev->device == 0x731f &&
+ adev->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
+ return 0;
+
/* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
DRM_WARN("System can't access extended configuration space, please check!!\n");