diff options
| author | Joel Fernandes <joelagnelf@nvidia.com> | 2025-11-10 22:34:21 +0900 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2025-11-14 20:25:57 +0900 |
| commit | bb58d1aee6081dba5f64eacf48993c077e99dd4a (patch) | |
| tree | 8a45b746224fd4471b809184e20049e4fbabe7eb /drivers/gpu/nova-core/regs.rs | |
| parent | 19b0a6e7c2be35f9b11c51c0c21c9a02c23252ff (diff) | |
gpu: nova-core: falcon: Add support to check if RISC-V is active
Add definition for RISCV_CPUCTL register and use it in a new falcon API
to check if the RISC-V core of a Falcon is active. It is required by
the sequencer to know if the GSP's RISCV processor is active.
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Message-ID: <20251110-gsp_boot-v9-13-8ae4058e3c0e@nvidia.com>
Diffstat (limited to 'drivers/gpu/nova-core/regs.rs')
| -rw-r--r-- | drivers/gpu/nova-core/regs.rs | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 41fdda8a0748..5d5ba766cd61 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -339,7 +339,12 @@ register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ PFalcon2Base[0x00000210[1]] { // PRISCV -register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] { +register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] { + 0:0 halted as bool; + 7:7 active_stat as bool; +}); + +register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalcon2Base[0x00000668] { 0:0 valid as bool; 4:4 core_select as bool => PeregrineCoreSelect; 8:8 br_fetch as bool; |