diff options
author | Miquel Raynal <miquel.raynal@bootlin.com> | 2025-10-03 17:23:18 +0200 |
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committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2025-10-03 17:23:18 +0200 |
commit | efebdf4b722143dc5073cee21276baf1673d451e (patch) | |
tree | 2c5beff85f5182fda177b0b0ef8bd0bab200a4ce /drivers/mtd/nand/raw/atmel/nand-controller.c | |
parent | 0473d5b964b755a55178f36cbcd832eb362cac03 (diff) | |
parent | 1001cc1171248ebb21d371fbe086b5d3f11b410b (diff) |
Merge tag 'nand/for-6.18' into mtd/next
* Raw NAND:
- Add support for Loongson-2K1000 and Loongson-2K0500 NAND controllers,
including extra features, such as chip select and 6-byte NAND ID
reading support.
- Drop the s3c2410 driver.
* SPI NAND:
- Important SPI NAND continuous read improvements and fixes.
- Add support for FudanMicro FM25S01A.
- Add support for continuous reads in Gigadevice vendor driver.
* ECC:
- Add support for the Realtek ECC engine.
This PR comes with the usual amount of various miscellaneous fixes.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'drivers/mtd/nand/raw/atmel/nand-controller.c')
-rw-r--r-- | drivers/mtd/nand/raw/atmel/nand-controller.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 84ab4a83cbd6..8c7b086456b5 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1240,7 +1240,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, const struct nand_interface_config *conf, struct atmel_smc_cs_conf *smcconf) { - u32 ncycles, totalcycles, timeps, mckperiodps; + u32 ncycles, totalcycles, timeps, mckperiodps, pulse; struct atmel_nand_controller *nc; int ret; @@ -1366,11 +1366,16 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, ATMEL_SMC_MODE_TDFMODE_OPTIMIZED; /* - * Read pulse timing directly matches tRP: + * Read pulse timing would directly match tRP, + * but some NAND flash chips (S34ML01G2 and W29N02KVxxAF) + * do not work properly in timing mode 3. + * The workaround is to extend the SMC NRD pulse to meet tREA + * timing. * - * NRD_PULSE = tRP + * NRD_PULSE = max(tRP, tREA) */ - ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); + pulse = max(conf->timings.sdr.tRP_min, conf->timings.sdr.tREA_max); + ncycles = DIV_ROUND_UP(pulse, mckperiodps); totalcycles += ncycles; ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles); @@ -1848,7 +1853,7 @@ atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc) static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc) { - struct device_node *np, *nand_np; + struct device_node *np; struct device *dev = nc->dev; int ret, reg_cells; u32 val; @@ -1875,7 +1880,7 @@ static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc) reg_cells += val; - for_each_child_of_node(np, nand_np) { + for_each_child_of_node_scoped(np, nand_np) { struct atmel_nand *nand; nand = atmel_nand_create(nc, nand_np, reg_cells); |