diff options
| author | Christian Bruel <christian.bruel@foss.st.com> | 2025-08-20 09:54:06 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-01 09:54:18 -0500 |
| commit | 151f3d29baf405bc203f0a02beb4d33604410943 (patch) | |
| tree | bd1b330ceb0a893968023bf13c316f2d94d5f040 /drivers/pci/controller/dwc/pcie-stm32.h | |
| parent | b8ef623f18da24ee9e1cf9bef66dacd2e8574902 (diff) | |
PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25
Add driver to configure the STM32MP25 SoC PCIe controller based on the
DesignWare PCIe core in endpoint mode. Controller support 2.5 and 5 GT/s
data rates and uses the common reference clock provided by the host.
The PCIe core_clk receives the pipe0_clk from the ComboPHY as input,
and the ComboPHY PLL must be locked for pipe0_clk to be ready.
Consequently, PCIe core registers cannot be accessed until the ComboPHY is
fully initialised and REFCLK is enabled and ready.
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
[mani: reworded description]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: squash in https://patch.msgid.link/20250902122641.269725-1-christian.bruel@foss.st.com
to remove redundant link_status checks]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250820075411.1178729-7-christian.bruel@foss.st.com
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-stm32.h')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-stm32.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-stm32.h b/drivers/pci/controller/dwc/pcie-stm32.h index 387112c4e42c..09d39f04e469 100644 --- a/drivers/pci/controller/dwc/pcie-stm32.h +++ b/drivers/pci/controller/dwc/pcie-stm32.h @@ -9,6 +9,7 @@ #define to_stm32_pcie(x) dev_get_drvdata((x)->dev) #define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8) +#define STM32MP25_PCIECR_EP 0 #define STM32MP25_PCIECR_LTSSM_EN BIT(2) #define STM32MP25_PCIECR_RC BIT(10) |