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authorDavid S. Miller <davem@davemloft.net>2017-01-25 23:13:45 -0500
committerDavid S. Miller <davem@davemloft.net>2017-01-25 23:13:45 -0500
commit1541f98cc252fac55d4e7cc933deddf341ff1710 (patch)
tree418ae6eb3373ade68fc733c32c6ecb20d77335cd /include/linux/brcmphy.h
parent434502930f59995f37fcc2c02cab79e059fb5043 (diff)
parent5e7bfa6cb0a94c673f6d565e58353366d88e2aa5 (diff)
Merge branch 'broadcom-phy-cleanup'
Rafał Miłecki says: ==================== net-next: Broadcom PHY driver cleanup I will probably need to use broadcom.ko for PHY connected to interface of bgmac supported device so I started looking at it willing to understand it better. I found AUXCTL part of the driver / lib a bit confusing and hard to read so I'm trying to clean it up a bit. I hope this patchset makes following AUXCTL operations much easier making it clear which defines are for registers and which for values. There is no functional change in this pachset. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/brcmphy.h')
-rw-r--r--include/linux/brcmphy.h16
1 files changed, 7 insertions, 9 deletions
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 295fb3e73de5..cf93f1399d3e 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -104,19 +104,17 @@
/*
* AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
*/
-#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
+#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
-#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
-#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
-#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
-#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
-#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
-#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
-#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
-#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN (1 << 4)
+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
+#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
+#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
+#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
/*