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authorQuentin Schulz <quentin.schulz@cherry.de>2025-02-25 12:53:29 +0100
committerHeiko Stuebner <heiko@sntech.de>2025-02-27 14:28:48 +0100
commit2db7d29c7b1629ced3cbab3de242511eb3c22066 (patch)
treee62f8559e7caec6fd6fb8bd4a518c44f0df6ca08 /include/linux/fpga/fpga-bridge.h
parent38f4aa34a5f737ea8588dac320d884cc2e762c03 (diff)
arm64: dts: rockchip: fix pinmux of UART0 for PX30 Ringneck on Haikou
UART0 pinmux by default configures GPIO0_B5 in its UART RTS function for UART0. However, by default on Haikou, it is used as GPIO as UART RTS for UART5. Therefore, let's update UART0 pinmux to not configure the pin in that mode, a later commit will make UART5 request the GPIO pinmux. Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Cc: stable@vger.kernel.org Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250225-ringneck-dtbos-v3-1-853a9a6dd597@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'include/linux/fpga/fpga-bridge.h')
0 files changed, 0 insertions, 0 deletions