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authorStephen Boyd <sboyd@kernel.org>2023-02-10 11:26:09 -0800
committerStephen Boyd <sboyd@kernel.org>2023-02-10 11:26:09 -0800
commitdede211f23e4b4a4d5d080c9923cc4df1e1fac87 (patch)
tree179750b44e50906eb3499561e643d5f6da952f59 /include
parent1b929c02afd37871d5afb9d498426f83432e71c2 (diff)
parent4e197ee880c24ecb63f7fe17449b3653bc64b03c (diff)
Merge tag 'clk-imx-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa: - Free the imx_uart_clocks even if imx_register_uart_clocks returns early - Get the stdout clocks count from device tree - Drop the clock count argument from imx_register_uart_clocks. - Keep the uart clocks on i.MX93 for when earlycon is used - Fix SPDX comment in i.MX6SLL clocks bindings header - Drop some unnecessary spaces from i.MX8ULP clocks bindings header - Add a new clk-gpr-mux clock type and use it on i.MX6Q to add ENET ref clocks - Add the imx_obtain_fixed_of_clock for allowing to add a clock that is not configured via devicetree - Fix the ENET1 gate configuration for i.MX6UL according to the reference manual - Add ENET refclock mux support for i.MX6UL * tag 'clk-imx-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx6ul: add ethernet refclock mux support clk: imx6ul: fix enet1 gate configuration clk: imx: add imx_obtain_fixed_of_clock() clk: imx6q: add ethernet refclock mux support clk: imx: add clk-gpr-mux driver dt-bindings: imx8ulp: clock: no spaces before tabs clk: imx6sll: add proper spdx license identifier clk: imx: imx93: invoke imx_register_uart_clocks clk: imx: remove clk_count of imx_register_uart_clocks clk: imx: get stdout clk count from device tree clk: imx: avoid memory leak
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h4
-rw-r--r--include/dt-bindings/clock/imx6sll-clock.h2
-rw-r--r--include/dt-bindings/clock/imx6ul-clock.h7
-rw-r--r--include/dt-bindings/clock/imx8ulp-clock.h4
-rw-r--r--include/linux/mfd/syscon/imx6q-iomuxc-gpr.h6
5 files changed, 16 insertions, 7 deletions
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index e20c43cc36f6..e5b2a1ba02bc 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -273,6 +273,8 @@
#define IMX6QDL_CLK_MMDC_P0_IPG 263
#define IMX6QDL_CLK_DCIC1 264
#define IMX6QDL_CLK_DCIC2 265
-#define IMX6QDL_CLK_END 266
+#define IMX6QDL_CLK_ENET_REF_SEL 266
+#define IMX6QDL_CLK_ENET_REF_PAD 267
+#define IMX6QDL_CLK_END 268
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
index f446710fe63d..494fd0c37fb5 100644
--- a/include/dt-bindings/clock/imx6sll-clock.h
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP.
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index 79094338e6f1..66239ebc0e23 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -256,7 +256,12 @@
#define IMX6UL_CLK_GPIO4 247
#define IMX6UL_CLK_GPIO5 248
#define IMX6UL_CLK_MMDC_P1_IPG 249
+#define IMX6UL_CLK_ENET1_REF_125M 250
+#define IMX6UL_CLK_ENET1_REF_SEL 251
+#define IMX6UL_CLK_ENET1_REF_PAD 252
+#define IMX6UL_CLK_ENET2_REF_SEL 253
+#define IMX6UL_CLK_ENET2_REF_PAD 254
-#define IMX6UL_CLK_END 250
+#define IMX6UL_CLK_END 255
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
index 953ecfe8ebcc..827404fadf5c 100644
--- a/include/dt-bindings/clock/imx8ulp-clock.h
+++ b/include/dt-bindings/clock/imx8ulp-clock.h
@@ -201,7 +201,7 @@
#define IMX8ULP_CLK_SAI7 2
#define IMX8ULP_CLK_SPDIF 3
#define IMX8ULP_CLK_ISI 4
-#define IMX8ULP_CLK_CSI_REGS 5
+#define IMX8ULP_CLK_CSI_REGS 5
#define IMX8ULP_CLK_PCTLD 6
#define IMX8ULP_CLK_CSI 7
#define IMX8ULP_CLK_DSI 8
@@ -212,7 +212,7 @@
#define IMX8ULP_CLK_GPU2D 13
#define IMX8ULP_CLK_GPU3D 14
#define IMX8ULP_CLK_DC_NANO 15
-#define IMX8ULP_CLK_CSI_CLK_UI 16
+#define IMX8ULP_CLK_CSI_CLK_UI 16
#define IMX8ULP_CLK_CSI_CLK_ESC 17
#define IMX8ULP_CLK_RGPIOD 18
#define IMX8ULP_CLK_DMA2_MP 19
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index d4b5e527a7a3..09c6b3184bb0 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -451,8 +451,10 @@
#define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0)
/* For imx6ul iomux gpr register field define */
-#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17)
-#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18)
+#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18)
+#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17)
+#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14)
+#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13)
#define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17)
#define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18)
#define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17)