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authorWenjing Liu <wenjing.liu@amd.com>2020-08-11 18:27:48 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-09-15 17:52:40 -0400
commit3fb068c3ec862b63b002e7818896cebea925e109 (patch)
tree59b28c74f9e4a9eca97b27eab453239c64d16d47 /lib/timerqueue.c
parent64fbb86d6b6f72c420dfcf23f82811a44d1c4670 (diff)
drm/amd/display: always use 100us for cr aux rd interval
[why] The cr training aux rd interval is modified without following specs requirements. According to the commit message the change was not intended to modify the value. Therefore it looks like it is caused by a typo in the change. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'lib/timerqueue.c')
0 files changed, 0 insertions, 0 deletions