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authorVille Syrjälä <ville.syrjala@linux.intel.com>2021-10-21 00:27:57 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2021-11-04 17:59:25 +0200
commit4d0d77de9af455aa949766ecad1ac3232e322020 (patch)
tree1275e02316634bf6d3c216589660aceb905e8fac /net/lapb/lapb_in.c
parent890b6ec4a522799d36bd10aee993059d771c06f4 (diff)
drm/i915: Split pre-skl primary plane update into noarm+arm pair
Chop i9xx_plane_update() into two halves. Fist half becomes the _noarm() variant, second part the _arm() variant. Fortunately I have already previously grouped the register writes into roughtly the correct order, so the split looks surprisingly clean. One slightly surprising fact was that the CHV pipe B PRIMPOS/SIZE registers are self arming unlike their pre-ctg DSPPOS/SIZE counterparts. In fact all the new CHV pipe B registers are self arming. Also we must remind ourselves that i830/i845 are a bit borked in that all of their plane registers are self-arming. I didn't do any i915_update_info measurements for this one alone. I'll get total numbers with the corrsponding sprite plane changes. v2: Don't break my precious i830/i845 Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211020212757.13517-1-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
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