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authorTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>2025-08-01 10:48:21 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-08-20 09:15:41 +0200
commit059db30b32e968fdbf6e416411fb78d481ff94bd (patch)
tree8155038781df17c8b8ba59c36c19fb298a69f58b /net/unix/sysctl_net_unix.c
parent6b234eda88d781d244094836afc37c90b57832f3 (diff)
clk: renesas: r9a09g047: Add DMAC clocks and resets
Add clock and reset entries for the Renesas RZ/G3E DMAC IPs. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250801084825.471011-2-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'net/unix/sysctl_net_unix.c')
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